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15.11 <A NAME="13829">
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References</H1>
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Page numbers in brackets after the reference indicate the location in the chapter body.</P>
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Cheng, C.-K., and Y.-C. A. Wei. 1991. “An improved two-way partitioning algorithm with stable performance.” <SPAN CLASS="BookTitle">
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, </SPAN>
Vol. 10, no. 12, pp. 1502–1511. Describes the ratio-cut algorithm. [<A HREF="CH15.7.htm#Cheng91" CLASS="XRef">
reference location</A>
]</P>
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Fiduccia, C. M., and R. M. Mattheyses. 1982. “A linear-time heuristic for improving network partitions.” In <SPAN CLASS="BookTitle">
Proceedings of the 19th Design Automation Conference,</SPAN>
pp. 175–181. Describes modification to Kernighan-Lin algorithm to reduce computation time. [<A HREF="CH15.7.htm#Fiduccia82" CLASS="XRef">
reference location</A>
]</P>
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Gajski, D. D., N. D. Dutt, A. C.-H. Wu, and S. Y.-L. Lin. 1992. <SPAN CLASS="BookTitle">
High-Level Synthesis: Introduction to Chip and System Design.</SPAN>
Norwell, MA: Kluwer. ISBN 0-7923-9194-2. TK7874.H52422. Chapter 6, Partitioning, is an introduction to system-level partitioning algorithms. It also includes a description of the system partitioning features of SpecSyn, a research tool developed at UC-Irvine. [<A HREF="CH15.a.htm#Gajski, 1992" CLASS="XRef">
reference location</A>
]</P>
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Goto, S., and T. Matsud. 1986. “Partitioning, assignment and placement.” In <SPAN CLASS="BookTitle">
Layout Design and Verification. </SPAN>
Vol. 4 of <SPAN CLASS="BookTitle">
Advances in CAD for VLSI</SPAN>
(T. Ohtsuki, Ed.) pp. 55–97, New York: Elsevier. [<A HREF="CH15.7.htm#Goto86" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
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Kernighan, B. W., and S. Lin. 1970. “An efficient heuristic procedure for partitioning graphs.” <SPAN CLASS="BookTitle">
Bell Systems Technical Journal, </SPAN>
Vol. 49, no. 2, February, pp. 291–307. The original description of the Kernighan–Lin partitioning algorithm. [<A HREF="CH15.7.htm#Kernighan70" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
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Kirkpatrick, S., et al. 1983. “Optimization by simulated annealing.” <SPAN CLASS="BookTitle">
Science, </SPAN>
Vol. 220, no. 4598, pp. 671–680. [<A HREF="CH15.7.htm#Kirkpatrick83" CLASS="XRef">
reference location</A>
]</P>
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Kucukcakar, K., and A. C. Parker, 1991. “CHOP: A constraint-driven system-level partitioner.” In <SPAN CLASS="BookTitle">
Proceedings of the 28th Design Automation Conference,</SPAN>
pp. 514–519. [<A HREF="CH15.a.htm#Kucukcakar91" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
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Lagnese, E., and D. Thomas. 1991. “Architectural partitioning for system level synthesis of integrated circuits.” <SPAN CLASS="BookTitle">
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, </SPAN>
Vol. 10, no. 7, pp. 847–860. [<A HREF="CH15.a.htm#Lagnese91" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
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Najm, F. N. 1994. “A survey of power estimation techniques in VLSI circuits.” <SPAN CLASS="BookTitle">
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, </SPAN>
Vol. 2, no. 4, pp. 446–455. 43 refs. [<A HREF="CH15.5.htm#Najm, 1994" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
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Preas, B. T., and P. G. Karger, 1988. “Placement, assignment and floorplanning.” In <SPAN CLASS="BookTitle">
Physical Design Automation of VLSI Systems </SPAN>
(B. T. Preas and M. J. Lorenzetti, Eds.), pp. 87–155. Menlo Park, CA: Benjamin-Cummings. ISBN 0-8053-0412-9. TK7874.P47. [<A HREF="CH15.a.htm#Preas88" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
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Rose, J., W. Klebsch, and J. Wolf, 1990. “Temperature measurement and equilibrium dynamics of simulated annealing placements.” <SPAN CLASS="BookTitle">
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, </SPAN>
Vol. 9, no. 3, pp. 253–259. Discusses ways to speed up simulated annealing. [<A HREF="CH15.7.htm#Rose90" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
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Schweikert, D. G., and B. W. Kernighan. 1979. “A proper model for the partitioning of electrical circuits.” In <SPAN CLASS="BookTitle">
Proceedings of the 9th Design Automation Workshop. </SPAN>
Points out the difference between nets and edges. [<A HREF="CH15.7.htm#Schweikert79" CLASS="XRef">
reference location</A>
, <A HREF="CH15.7.htm#Schweikert79" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
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Sechen, C. 1988. <SPAN CLASS="BookTitle">
VLSI Placement and Global Routing Using Simulated Annealing. </SPAN>
New York: Kluwer. Introduction; The Simulated Annealing Algorithm; Placement and Global Routing of Standard Cell Integrated Circuits; Macro/Custom Cell Chip-Planning, Placement, and Global Routing; Average Interconnection Length Estimation; Interconnect-Area Estimation for Macro Cell Placements; An Edge-Based Channel Definition Algorithm for Rectilinear Cells; A Graph-Based Global Router Algorithm; Conclusion; Island-Style Gate Array Placement. [<A HREF="CH15.a.htm#Sechen88" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
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</A>
Sedgewick, R. 1988. <SPAN CLASS="BookTitle">
Algorithms.</SPAN>
Reading, MA: Addison-Wesley. ISBN 0-201-06673-4. QA76.6.S435. Reference for basic sorting and graph-searching algorithms. [<A HREF="CH15.2.htm#Sedgewick88" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
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</A>
Sherwani, N. A. 1993. <SPAN CLASS="BookTitle">
Algorithms for VLSI Physical Design Automation.</SPAN>
Norwell, MA: Kluwer. ISBN 0-7923-9294-9. TK874.S455. [<A HREF="CH15.a.htm#Sherwani93" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
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</A>
Smailagic, A., et al. 1995. “Benchmarking an interdisciplinary concurrent design methodology for electronic/mechanical systems.” In <SPAN CLASS="BookTitle">
Proceedings of the 32nd Design Automation Conference.</SPAN>
San Francisco. Describes the evolution of the <A NAME="marker=191918">
</A>
VuMan wearable computer. Includes some interesting measures of the complexity of system design. [<A HREF="CH15.9.htm#Smailagic95" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
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Veendrick, H. J. M. 1984. “Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits.” <SPAN CLASS="BookTitle">
IEEE Journal of Solid-State Circuits, </SPAN>
Vol. SC-19, no. 4, pp. 468–473. [<A HREF="CH15.5.htm#[Veendrick, 1984]" CLASS="XRef">
reference location</A>
, <A HREF="CH15.9.htm#Veendrick, 1984" CLASS="XRef">
reference location</A>
]</P>
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