ch15.9.htm

介绍asci设计的一本书

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1/(2f)</P>
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d<SPAN CLASS="EquationVariables">
V</SPAN>
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=</P>
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<SPAN CLASS="EquationVariables">
f</SPAN>
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<SPAN CLASS="BigMath">
&Uacute;</SPAN>
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<SPAN CLASS="EquationVariables">
CV</SPAN>
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&#8211;&#8211;</P>
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d<SPAN CLASS="EquationVariables">
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=</P>
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0.5 <SPAN CLASS="EquationVariables">
fCV</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
<SUP CLASS="Superscript">
2</SUP>
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(15.24)</P>
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0</P>
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d<SPAN CLASS="EquationVariables">
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<P CLASS="Exercise">
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During the second half-period of the input signal the <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistor is off, so that there can be no power dissipation in the power supply. The power dissipation that occurs in the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor must come from the stored energy in the capacitor&#8212;which is accounted for in the equation. In both cases the total power dissipation should be 1/2(<SPAN CLASS="EquationVariables">
fCV</SPAN>
<SUP CLASS="Superscript">
2</SUP>
), not (<SPAN CLASS="EquationVariables">
fCV</SPAN>
<SUP CLASS="Superscript">
2</SUP>
) as we have stated in Eq. <A HREF="CH15.5.htm#42545" CLASS="XRef">
15.4</A>
. Point out the errors in both of these arguments. (If you are interested in situations in which these equations do hold, you can search for the term <A NAME="marker=161613">
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adiabatic logic.)</P>
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15.17&nbsp;<A NAME="27714">
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(Short-circuit power dissipation, 30  min.) Prove Eq. <A HREF="CH15.5.htm#23327" CLASS="XRef">
15.5</A>
 as follows: The input to a CMOS inverter is a linear ramp with rise time <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
rf</SUB>
. Calculate the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor current as a function of the input voltage, <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="Subscript">
in</SUB>
, assuming the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor turns on when <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="Subscript">
in</SUB>
 = <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
t</SUB>
<SPAN CLASS="EquationVariables">
n</SPAN>
 and the current reaches a maximum when <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="Subscript">
in</SUB>
 = <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD </SUB>
/ 2 at <SPAN CLASS="EquationVariables">
t</SPAN>
 = <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
rf</SUB>
 / 2.</P>
<P CLASS="Exercise">
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The transistor current is given by Eq.&nbsp;2.9. Assume <SPAN CLASS="Symbol">
b</SPAN>
 = (<SPAN CLASS="EquationNumber">
W/L</SPAN>
)<SPAN CLASS="Symbol">
m</SPAN>
<SPAN CLASS="EquationNumber">
Cox</SPAN>
 is the same for both <SPAN CLASS="EmphasisPrefix">
p</SPAN>
- and <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistors, the magnitude of the threshold voltages | V<SUB CLASS="Subscript">
t</SUB>
<SUB CLASS="SubscriptVariable">
n</SUB>
 | are assumed equal for both transistor types, and <SPAN CLASS="Symbol">
t</SPAN>
 is the rise time and fall time (assumed equal) of the input signal.</P>
<P CLASS="Exercise">
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Show that for a CMOS inverter (Eq. <A HREF="CH15.5.htm#23327" CLASS="XRef">
15.5</A>
):  </P>
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2</SUB>
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=</P>
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(1/12)<SPAN CLASS="Symbol">
b </SPAN>
<SPAN CLASS="EquationVariables">
f t</SPAN>
<SUB CLASS="SubscriptVariable">
rf</SUB>
<SPAN CLASS="EquationVariables">
(V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
 &#8211; 2 V<SUB CLASS="Subscript">
t</SUB>
<SUB CLASS="SubscriptVariable">
n</SUB>
)<SUP CLASS="Superscript">
3</SUP>
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(15.25)</P>
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<P CLASS="Exercise">
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where <SPAN CLASS="Symbol">
b</SPAN>
 = (<SPAN CLASS="EquationNumber">
W/L</SPAN>
)<SPAN CLASS="Symbol">
m</SPAN>
<SPAN CLASS="EquationNumber">
Cox</SPAN>
 is the same for both <SPAN CLASS="EmphasisPrefix">
p</SPAN>
- and <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistors, the magnitude of the threshold voltages | V<SUB CLASS="Subscript">
t</SUB>
<SUB CLASS="SubscriptVariable">
n</SUB>
 | are assumed equal for both transistors, and <SPAN CLASS="Symbol">
t</SPAN>
 is the rise time and fall time (assumed equal) of the input signal [<A NAME="Veendrick, 1984">
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Veendrick, 1984].</P>
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15.18&nbsp;(Connectivity matrix, 10  min.)&nbsp;Find the connectivity matrix for the ATM Connection Simulator shown in <A HREF="CH15.6.htm#11762" CLASS="XRef">
Figure&nbsp;15.5</A>
. Use the following scheme to number the blocks and ordering of the matrix rows and columns: 1 = Personal Computer, 2 = Intel 80186, 3 = UTOPIA receiver, 4 = UTOPIA transmitter, 5 = Header remapper and screener, 6 = Remapper SRAM, . . . 15 = Random-number and bit error rate generator, 16 = Random-variable generator. All buses are labeled with their width except for two single connections (the arrows).</P>
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15.19&nbsp;(K&#8211;L algorithm, 15  min.)</P>
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<LI CLASS="ExercisePartFirst">
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a.&nbsp;Draw the network graph for the following connectivity matrix:  </LI>
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0 0 0 0 0 0 1 0 0 0</P>
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0 0 0 0 0 1 0 1 0 0</P>
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0 0 0 1 0 0 0 1 0 0</P>
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0 0 1 0 1 0 0 0 1 0</P>
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