📄 ch15.9.htm
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Manufacturer</SPAN>
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Chip</SPAN>
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<SPAN CLASS="TableHeads">
Package</SPAN>
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Function</SPAN>
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<A NAME="pgfId=80378">
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<SPAN CLASS="TableHeads">
Comment</SPAN>
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<A NAME="pgfId=80380">
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HP</P>
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<A NAME="pgfId=80382">
</A>
87411AAE</P>
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<P CLASS="TableLeft">
<A NAME="pgfId=80384">
</A>
24-pin DIP </P>
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<P CLASS="TableLeft">
<A NAME="pgfId=80386">
</A>
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<P CLASS="TableLeft">
<A NAME="pgfId=80388">
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<A NAME="pgfId=80390">
</A>
Intel</P>
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<P CLASS="TableLeft">
<A NAME="pgfId=80392">
</A>
L7220048</P>
</TD>
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<P CLASS="TableLeft">
<A NAME="pgfId=80394">
</A>
40-pin DIP </P>
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<P CLASS="TableLeft">
<A NAME="pgfId=80396">
</A>
EPROM (9/3/87) </P>
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<A NAME="pgfId=80398">
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Boot commands </P>
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<P CLASS="TableLeft">
<A NAME="pgfId=80400">
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Chips</P>
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<A NAME="pgfId=80402">
</A>
7014-0093</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=80404">
</A>
80-pin quad flat pack</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=80406">
</A>
Custom ASIC</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=80408">
</A>
</P>
</TD>
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<P CLASS="TableLeft">
<A NAME="pgfId=80410">
</A>
Intel</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=80412">
</A>
80286-12</P>
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<P CLASS="TableLeft">
<A NAME="pgfId=80414">
</A>
68-pin package</P>
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<P CLASS="TableLeft">
<A NAME="pgfId=80416">
</A>
Microprocessor</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=80418">
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CPU </P>
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<P CLASS="TableLeft">
<A NAME="pgfId=80420">
</A>
TI</P>
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<P CLASS="TableLeft">
<A NAME="pgfId=80422">
</A>
AS00</P>
</TD>
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<P CLASS="TableLeft">
<A NAME="pgfId=80424">
</A>
14-pin DIP </P>
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<P CLASS="TableLeft">
<A NAME="pgfId=80426">
</A>
Quad 2-input NAND gate</P>
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<P CLASS="TableLeft">
<A NAME="pgfId=80428">
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Addressing</P>
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<P CLASS="TableLeft">
<A NAME="pgfId=80430">
</A>
</P>
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<A NAME="pgfId=80432">
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S74F08D</P>
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<P CLASS="TableLeft">
<A NAME="pgfId=80434">
</A>
14-pin DIP </P>
</TD>
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<P CLASS="TableLeft">
<A NAME="pgfId=80436">
</A>
Quad 2-input AND gate</P>
</TD>
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<P CLASS="TableLeft">
<A NAME="pgfId=80438">
</A>
Addressing</P>
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<P CLASS="TableLeft">
<A NAME="pgfId=80440">
</A>
</P>
</TD>
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<P CLASS="TableLeft">
<A NAME="pgfId=80442">
</A>
F74F51</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=80444">
</A>
14-pin DIP </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=80446">
</A>
AOI gate</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=80448">
</A>
Addressing</P>
</TD>
</TR>
</TABLE>
<P CLASS="ExerciseHead">
<A NAME="pgfId=16719">
</A>
15.12 <A NAME="40515">
</A>
(Estimates, 60 min.) System partitioning is not exact science. Estimate:</P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=16720">
</A>
a. The power developed by a grasshopper, in watts (from a Cambridge University entrance exam).</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=16721">
</A>
b. The number of doors in New York City.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=16726">
</A>
c. The number of grains of sand on Hawaii’s beaches.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=16727">
</A>
d. The total length of the roads in the continental United States in kilometers.</LI>
</UL>
<P CLASS="Exercise">
<A NAME="pgfId=38720">
</A>
In each case: (i) Provide an equation that depends on parameters and symbols that you define. (ii) List the parameters in your equation, and the values that you assume with their uncertainty. (iii) Give the answer as a number (with units where necessary). (iv) Include a numerical estimate of the uncertainty in your answer.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=161733">
</A>
15.13 (Pad-limited and core-limited die, 10 min.) As the number of I/O pads increases, an ASIC can become <A NAME="marker=161736">
</A>
pad-limited. The spacing between I/O pads is determined by mechanical limitations of the equipment used for bonding—usually 2–5 mil (a mil is a thousandth of an inch). In a pad-limited design the number of pads around the outer edge of the die determines the die size, not the number of gates (see <A HREF="CH15.9.htm#22512" CLASS="XRef">
Figure 15.12</A>
). For the pad-limited design, shown in <A HREF="CH15.9.htm#22512" CLASS="XRef">
Figure 15.12</A>
(a), the price per I/O pad is more important than the price per gate. When we have a lot of logic but few I/O pads, we have a <A NAME="marker=161753">
</A>
core-limited design—the opposite of a pad-limited ASIC—as shown in <A HREF="CH15.9.htm#22512" CLASS="XRef">
Figure 15.12</A>
(b). For a given number of I/O pads and a pad-limited design, all the different ASIC types will have the same die size, determined by a graph such as the one shown in <A HREF="CH15.9.htm#22512" CLASS="XRef">
Figure 15.12</A>
(c). If I/O pad spacing is 5 mil and gate density is 1.0 gate/mil<SUP CLASS="Superscript">
2</SUP>
, when does an ASIC becomes pad-limited? Express your answer as a function of the number of gates, <SPAN CLASS="EquationVariables">
G</SPAN>
, and the number of I/Os, <SPAN CLASS="EquationVariables">
I</SPAN>
.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=161746">
</A>
</P>
<DIV>
<IMG SRC="CH15-17.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=161749">
</A>
FIGURE 15.12 <A NAME="22512">
</A>
Die size. (a) A pad-limited die, the die size is determined by the number of I/O pads. (b) A core-limited die, the die size is limited by the amount of logic in the core. (c) For a given pad spacing we can determine the die size for a pad-limited die.</P>
</TD>
</TR>
</TABLE>
<P CLASS="ExerciseHead">
<A NAME="pgfId=38722">
</A>
15.14 <A NAME="38862">
</A>
(Estimating ASIC size, 120 min.) Let us pretend we are going to build a laptop SPARCstation. We need to drastically reduce the number of chips used in the desktop system. Focus on the I/O subsystems in <A HREF="CH15.3.htm#20233" CLASS="XRef">
Figure 15.2</A>
(chip labels are shown in parentheses): LANCE Ethernet controller (14), 3C90 SCSI controller (15), 85C30 serial port controller (16, 17), 79C30 ISDN interface (18), and 82072 floppy-disk controller (19). Consider combining these functions into a single custom ASIC.</P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=32546">
</A>
a. Collect as much data as you can on the ASSP chips (14–19) that are currently used in the SPARCstation 1, similar to that presented in <A HREF="CH15.4.htm#34677" CLASS="XRef">
Table 15.5</A>
. National Semiconductor, Texas Instruments, AMD, Intel, and Motorola produce these or similar chips. You will need one or more of their ASSP data books. Try to find the pin count, power dissipation, and gate count for each chip. If you can’t find one of these parameters, make an estimate and explain your assumptions.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=32547">
</A>
b. Using your data, make an estimate of the size, power dissipation, and pin count of the ASIC to replace chips 14–19 in <A HREF="CH15.4.htm#13642" CLASS="XRef">
Figure 15.2</A>
.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=32548">
</A>
c. As a sanity check compare your results with the DMA2 Ethernet, SCSI, and parallel port chip in the SPARCstation 10 (see <A HREF="CH15.4.htm#13642" CLASS="XRef">
Table 15.2</A>
). This is a 30 k-gate array in a 160-pin quad flat pack.</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=161561">
</A>
15.15 <A NAME="21363">
</A>
(Power dissipation, 20 min.) If a Pentium microprocessor dissipates 5 W and, on average, 20 percent of the circuit nodes toggle every clock cycle </P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=188784">
</A>
a. Calculate the total capacitance of all the circuit nodes in picofarads if the clock frequency is 100 MHz and <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
= 5 V.<SPAN CLASS="Bold">
</SPAN>
</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=188790">
</A>
b. If half of this is due to interconnect capacitance at 2 pFcm<SUP CLASS="Superscript">
–1</SUP>
, what is the total length of interconnect? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=188797">
</A>
c. If there are 100 I/Os driving an average of 20 pF load off-chip at an average frequency of 50 MHz, what is the power dissipation in the I/Os? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=188798">
</A>
d. A Pentium chip contains about 3 <SPAN CLASS="Symbol">
¥</SPAN>
10<SUP CLASS="Superscript">
6</SUP>
transistors. How many gates is this? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=188793">
</A>
e. How many gates are switching on average every clock cycle?</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=161597">
</A>
15.16 <A NAME="15567">
</A>
(Parasitic power dissipation, 20 min.) Consider the following arguments: The energy stored in a capacitor is 1/2(<SPAN CLASS="EquationVariables">
CV</SPAN>
<SUP CLASS="Superscript">
2</SUP>
) (measured in joules). Suppose we charge and discharge a capacitance <SPAN CLASS="EquationVariables">
C</SPAN>
between zero and <SPAN CLASS="EquationVariables">
V</SPAN>
volts at a frequency <SPAN CLASS="EquationVariables">
f</SPAN>
. We have to replace this energy <SPAN CLASS="EquationVariables">
f</SPAN>
times per second and we shall dissipate a power (measured in watts) equal to </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=205373">
</A>
P</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=205375">
</A>
=</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnLeft">
<A NAME="pgfId=205377">
</A>
0.5 f<SPAN CLASS="EquationVariables">
CV</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
<SUP CLASS="Superscript">
2</SUP>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnLeft">
<A NAME="pgfId=205379">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=205381">
</A>
(15.23)</P>
</TD>
</TR>
</TABLE>
<P CLASS="Exercise">
<A NAME="pgfId=161603">
</A>
When the <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistor in an inverter is charging a capacitance, <SPAN CLASS="EquationVariables">
C</SPAN>
, at a frequency, <SPAN CLASS="EquationVariables">
f</SPAN>
, the current through the transistor is <SPAN CLASS="EquationVariables">
C</SPAN>
(d<SPAN CLASS="EquationVariables">
V</SPAN>
/d<SPAN CLASS="EquationVariables">
t</SPAN>
), the power dissipation is <SPAN CLASS="EquationVariables">
CV</SPAN>
(d<SPAN CLASS="EquationVariables">
V</SPAN>
/d<SPAN CLASS="EquationVariables">
t</SPAN>
) for one-half the period of the input, <SPAN CLASS="EquationVariables">
t</SPAN>
= 1/(2<SPAN CLASS="EquationVariables">
f</SPAN>
). The power dissipated in the <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistor is thus </P>
<TABLE>
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<P CLASS="TableEqnRight">
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</A>
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<P CLASS="TableEqnCenter">
<A NAME="pgfId=205475">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=205491">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnRight">
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