ch15.4.htm

介绍asci设计的一本书

<A NAME="pgfId=172706">
 </A>
Low-speed decrementer</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=172708">
 </A>
14,000</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=172710">
 </A>
4.6E + 05</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=172712">
 </A>
9.2E + 05</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=172714">
 </A>
Low-speed incrementer</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=172716">
 </A>
14,000</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=172718">
 </A>
4.6E + 05</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=172720">
 </A>
9.2E + 05</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=172722">
 </A>
Low-speed incrementer/decrementer</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=172724">
 </A>
20,000</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLast">
<A NAME="pgfId=172726">
 </A>
6.5E + 05</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLast">
<A NAME="pgfId=172728">
 </A>
1.3E + 06</P>
</TD>
</TR>
</TABLE>
</UL>
<P CLASS="Body">
<A NAME="pgfId=172729">
 </A>
Most datapath elements have an area per bit that depends on the number of bits in the datapath (the <A NAME="marker=172730">
 </A>
datapath width). Sometimes this dependency is linear (for the multipliers and the barrel shifter, for example); in other elements it depends on the logarithm (to base 2) of the datapath width (the leading one, all ones, and zero detectors, for example). In some elements you might expect there to be a dependency on datapath width, but it is small (the comparators are an example).</P>
<P CLASS="Body">
<A NAME="pgfId=172805">
 </A>
The area estimates given in <A HREF="CH15.4.htm#39404" CLASS="XRef">
Table&nbsp;15.4</A>
 can be misleading. The exact size of an adder, for example, depends on the architecture: carry-save, carry-select, carry-lookahead, or ripple-carry (which depends on the speed you require). These area figures also exclude the routing between datapath elements, which is difficult to predict&#8212;it will depend on the number and size of the datapath elements, their type, and how much logic is random and how much is datapath.</P>
<P CLASS="Body">
<A NAME="pgfId=172811">
 </A>
<A HREF="CH15.4.htm#23242" CLASS="XRef">
Figure&nbsp;15.3</A>
(a) shows the typical size of <A NAME="marker=172810">
 </A>
SRAM constructed on an ASIC. These figures are based on the use of a RAM compiler (as opposed to building memory from flip-flops or latches) using a standard CMOS ASIC process, typically using a six-transistor cell. The actual size of a memory will depend on (1) the required access time, (2) the use of synchronous or asynchronous read or write, (3) the number and type of ports (read&#8211;write), (4) the use of special design rules, (5) the number of interconnect layers available, (6) the RAM architecture (number of devices in RAM cell), and (7) the process technology (active pull-up devices or pull-up resistors). </P>
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<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=83528">
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(a)</P>
<DIV>
<IMG SRC="CH15-3.gif">
</DIV>
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<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=185212">
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(b)</P>
<DIV>
<IMG SRC="CH15-4.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=175695">
 </A>
FIGURE&nbsp;15.3&nbsp;<A NAME="23242">
 </A>
(a)&nbsp;ASIC memory size. These figures are for static RAM constructed using compilers in a 2LM ASIC process, but with no special memory design rules. The actual area of a RAM will depend on the speed and number of read&#8211;write ports. (b)&nbsp;Multiplier size for a 2LM process. The actual area will depend on the multiplier architecture and speed.</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=83521">
 </A>
The maximum size of SRAM in <A HREF="CH15.4.htm#23242" CLASS="XRef">
Figure&nbsp;15.3</A>
(a) is 32 k-bit, which occupies approximately 6.0 <SPAN CLASS="Symbol">
&#165;</SPAN>
 10<SUP CLASS="Superscript">
7 </SUP>
 <SPAN CLASS="Symbol">
l</SPAN>
<SUP CLASS="Superscript">
2</SUP>
. In a 0.5<SPAN CLASS="Symbol">
 m</SPAN>
m process (with <SPAN CLASS="Symbol">
l</SPAN>
 = 0.25 <SPAN CLASS="Symbol">
m</SPAN>
m), the area of a 32 k-bit SRAM is 6.0 <SPAN CLASS="Symbol">
&#165;</SPAN>
 10<SUP CLASS="Superscript">
7</SUP>
 <SPAN CLASS="Symbol">
&#165;</SPAN>
 0.25 <SPAN CLASS="Symbol">
&#165;</SPAN>
 0.25 = 3.75 <SPAN CLASS="Symbol">
&#165;</SPAN>
 10<SUP CLASS="Superscript">
6</SUP>
 <SPAN CLASS="Symbol">
m</SPAN>
m<SUP CLASS="Superscript">
2</SUP>
 (or about 2 mm on a side&#8212;a large piece of silicon). If you need an SRAM that is larger than this, you probably need to consult with your ASIC vendor to determine the best way to implement a large on-chip memory. <A HREF="CH15.4.htm#23242" CLASS="XRef">
Figure&nbsp;15.3</A>
(b) shows the typical sizes for <A NAME="marker=99534">
 </A>
multipliers. Again the actual multiplier size will depend on the architecture (Booth encoding, Wallace tree, and so on), the process technology, and design rules. <A HREF="CH15.4.htm#34677" CLASS="XRef">
Table&nbsp;15.5</A>
 shows some estimated gate counts for medium-size functions corresponding to some popular ASSP devices. </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="4">
<P CLASS="TableTitle">
<A NAME="pgfId=146806">
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TABLE&nbsp;15.5&nbsp;<A NAME="34677">
 </A>
Gate size estimates for popular ASSP functions.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=146814">
 </A>
ASSP device</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=146816">
 </A>
<SPAN CLASS="TableHeads">
Function</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=146818">
 </A>
Gate estimate</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=146820">
 </A>
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146822">
 </A>
   8251A</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=146824">
 </A>
Universal synchronous/asynchronous receiver/transmitter (USART)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146826">
 </A>
2900</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146828">
 </A>
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146830">
 </A>
 8253</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=146832">
 </A>
Programmable interval timer</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146834">
 </A>
5680</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146836">
 </A>
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146838">
 </A>
   8255A</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=146840">
 </A>
Programmable peripheral interface</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146842">
 </A>
784&#8211;1403</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146844">
 </A>
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146846">
 </A>
  8259</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=146848">
 </A>
Programmable interrupt controller</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146850">
 </A>
2205</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146852">
 </A>
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146854">
 </A>
 8237</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=146856">
 </A>
Programmable DMA controller</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146858">
 </A>
5100</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146860">
 </A>
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146862">
 </A>
 8284</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=146864">
 </A>
Clock generator/driver</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146866">
 </A>
  99</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146868">
 </A>
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=147013">
 </A>
 8288</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=147015">
 </A>
Bus controller</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=147017">
 </A>
 250</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=147019">
 </A>
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=147005">
 </A>
 8254</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=147007">
 </A>
Programmable interval timer</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=147009">
 </A>
3500</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=147011">
 </A>
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146997">
 </A>
 6845</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=146999">
 </A>
CRT controller</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=147001">
 </A>
2843</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=147003">
 </A>
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146989">
 </A>
87030</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=146991">
 </A>
SCSI controller</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146993">
 </A>
3600</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146995">
 </A>
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146981">
 </A>
87012</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=146983">
 </A>
Ethernet controller</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146985">
 </A>
3900</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146987">
 </A>
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146973">
 </A>
 2901</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=146975">
 </A>
4 bit ALU</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146977">
 </A>
 917</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146979">
 </A>
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146965">
 </A>
 2902</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=146967">
 </A>
Carry-lookahead ALU</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146969">
 </A>
  33</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146971">
 </A>
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146957">
 </A>
 2904</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=146959">
 </A>
Status and shift control</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146961">
 </A>
 500</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146963">
 </A>
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146949">
 </A>
 2910</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=146951">
 </A>
12- bit microprogram controller</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146953">
 </A>
1100</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=146955">
 </A>
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="4">
<P CLASS="TableLeft">
<A NAME="pgfId=146887">
 </A>
<SPAN CLASS="Emphasis">
Source: </SPAN>
Fujitsu channelless gate-array data book, AU and CG21 series.</P>
</TD>
</TR>
</TABLE>
<HR>
<DIV CLASS="footnotes">
<DIV CLASS="footnote">
<P CLASS="TableFootLast">
<SPAN CLASS="footnoteNumber">
1.</SPAN>
<A NAME="pgfId=195287">
 </A>
2LM = two-level metal; 3LM = three-level metal.</P>
</DIV>
<DIV CLASS="footnote">
<P CLASS="TableFootLast">
<SPAN CLASS="footnoteNumber">
2.</SPAN>
<A NAME="pgfId=182077">
 </A>
Area estimates are for a two-level metal (2 LM) process. Areas for a three-level metal (3LM) process are approximately 0.75 to 1.0 times these figures.</P>
</DIV>
</DIV>
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