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<TITLE> PROGRAMMABLE&nbsp;ASIC I/O CELLS</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->



<DIV>

<P>[&nbsp;<A HREF="../../ASICs.htm#anchor749424">Chapter &nbsp;Index</A>&nbsp;]&nbsp;[&nbsp;<A HREF="CH06.1.htm">Next&nbsp;page</A>&nbsp;]</P><!--#include file="AmazonAsic.html"--><HR></DIV>

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<H1 CLASS="ChapterTitle">

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PROGRAMMABLE&nbsp;<BR>

ASIC I/O CELLS</H1>

<P CLASS="BodyAfterHead">

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All programmable ASICs contain some type of <A NAME="marker=82693">

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<SPAN CLASS="Definition">

input/output cell</SPAN>

 (<A NAME="marker=82694">

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<SPAN CLASS="Definition">

I/O cell</SPAN>

). These I/O cells handle driving logic signals off-chip, receiving and conditioning external inputs, as well as handling such things as electrostatic protection. This chapter explains the different types of I/O cells that are used in programmable ASICs and their functions.</P>

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The following are different types of I/O requirements.</P>

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DC output.</SPAN>

 Driving a resistive load at DC or low frequency (less than 1 MHz). Example loads are light-emitting diodes (LEDs), relays, small motors, and such. Can we supply an output signal with enough voltage, current, power, or energy?</LI>

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AC output.</SPAN>

 Driving a capacitive load with a high-speed (greater than 1 MHz) logic signal off-chip. Example loads are other logic chips, a data or address bus, ribbon cable. Can we supply a valid signal fast enough?</LI>

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<A NAME="pgfId=30772">

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DC input. </SPAN>

Example sources are a switch, sensor, or another logic chip. Can we correctly interpret the digital value of the input?</LI>

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<A NAME="pgfId=30773">

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AC input.</SPAN>

 Example sources are high-speed logic signals (higher than 1 MHz) from another chip. Can we correctly interpret the input quickly enough?</LI>

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<A NAME="pgfId=30774">

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Clock input.</SPAN>

 Examples are system clocks or signals on a synchronous bus. Can we transfer the timing information from the input to the appropriate places on the chip correctly and quickly enough?</LI>

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Power input.</SPAN>

 We need to supply power to the I/O cells and the logic in the core, without introducing voltage drops or noise. We may also need a separate power supply to program the chip.</LI>

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These issues are common to all FPGAs (and all ICs) so that the design of FPGA I/O cells is driven by the I/O requirements as well as the programming technology.</P>

<H2 CLASS="Heading1TOC">

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6.1&nbsp;DC Output</A>

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<A HREF="CH06.2.htm#pgfId=18985" CLASS="Hypertext">

6.2&nbsp;AC Output</A>

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<A HREF="CH06.3.htm#pgfId=80970" CLASS="Hypertext">

6.3&nbsp;DC Input </A>

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<A HREF="CH06.4.htm#pgfId=19221" CLASS="Hypertext">

6.4&nbsp;AC Input</A>

</H2>

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<A HREF="CH06.5.htm#pgfId=19037" CLASS="Hypertext">

6.5&nbsp;Clock Input</A>

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<A HREF="CH06.6.htm#pgfId=19053" CLASS="Hypertext">

6.6&nbsp;Power Input</A>

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<A HREF="CH06.7.htm#pgfId=77984" CLASS="Hypertext">

6.7&nbsp;Xilinx I/O Block</A>

</H2>

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<A HREF="CH06.8.htm#pgfId=81032" CLASS="Hypertext">

6.8&nbsp;Other I/O Cells</A>

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6.9&nbsp;Summary</A>

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6.10&nbsp;Problems</A>

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<A HREF="CH06.b.htm#pgfId=78893" CLASS="Hypertext">

6.11&nbsp;Bibliography</A>

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<A HREF="CH06.c.htm#pgfId=4957" CLASS="Hypertext">

6.12&nbsp;References</A>

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</DIV>

<HR><P>[&nbsp;<A A HREF="../../ASICs.htm#anchor749424">Chapter &nbsp;Index</A>&nbsp;]&nbsp;[&nbsp;<A HREF="CH06.1.htm">Next&nbsp;page</A>&nbsp;]</P></BODY>



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