📄 ch06.4.htm
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<P CLASS="TableEqnRight">
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MTBU</P>
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=</P>
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–––––––––––––––––––––</P>
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=</P>
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5.2 <SPAN CLASS="Symbol">
¥</SPAN>
10<SUP CLASS="Superscript">
8</SUP>
seconds ,</P>
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(6.5)</P>
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<A NAME="pgfId=107217">
</A>
(100 <SPAN CLASS="Symbol">
¥</SPAN>
10<SUP CLASS="Superscript">
6</SUP>
)(1 <SPAN CLASS="Symbol">
¥</SPAN>
10<SUP CLASS="Superscript">
6</SUP>
)(0.1)</P>
</TD>
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</A>
</P>
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</A>
<SUB CLASS="Subscript">
</SUB>
</P>
</TD>
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<P CLASS="BodyAfterHead">
<A NAME="pgfId=19099">
</A>
or about 16 years (10<SUP CLASS="Superscript">
8</SUP>
seconds is three years, and a day is 10<SUP CLASS="Superscript">
5</SUP>
seconds). An MTBU of 16 years may seem safe, but suppose we have a 64-bit input bus using 64 flip-flops. If each flip-flop has an MTBU of 16 years, our system-level MTBF is three months. If we ship 1000 systems we would have an average of 10 systems failing every day. What can we do?</P>
<P CLASS="Body">
<A NAME="pgfId=19102">
</A>
The parameter <SPAN CLASS="Symbol">
t</SPAN>
<SUB CLASS="SubscriptVariable">
c</SUB>
is the inverse of the <SPAN CLASS="Definition">
gain–bandwidth product</SPAN>
<A NAME="marker=77309">
</A>
, <SPAN CLASS="EquationVariables">
GB</SPAN>
<A NAME="marker=77310">
</A>
, of the sampler at the instant of sampling. It is a constant that is independent of whether we are sampling a positive or negative data edge. It may be determined by a small-signal analysis of the sampler at the sampling instant or by measurement. It cannot be determined by simulating the transient response of the flip-flop to a metastable event since the gain and bandwidth both normally change as a function of time. We cannot change <SPAN CLASS="Symbol">
t</SPAN>
<SUB CLASS="SubscriptVariable">
c</SUB>
.</P>
<P CLASS="Body">
<A NAME="pgfId=61123">
</A>
The parameter <SPAN CLASS="EquationNumber">
T</SPAN>
<SUB CLASS="Subscript">
0</SUB>
(units of time) is a function of the process technology and the circuit design. It may be different for sampling a positive or negative data edge, but normally only one value of <SPAN CLASS="EquationNumber">
T</SPAN>
<SUB CLASS="Subscript">
0</SUB>
is given. Attempts have been made to calculate <SPAN CLASS="EquationNumber">
T</SPAN>
<SUB CLASS="Subscript">
0</SUB>
and to relate it to a physical quantity. The best method is by measurement or simulation of metastable events. We cannot change <SPAN CLASS="EquationNumber">
T</SPAN>
<SUB CLASS="Subscript">
0</SUB>
.</P>
<P CLASS="Body">
<A NAME="pgfId=61130">
</A>
Given a good flip-flop or latch design, <SPAN CLASS="Symbol">
t</SPAN>
<SUB CLASS="SubscriptVariable">
c</SUB>
and <SPAN CLASS="EquationNumber">
T</SPAN>
<SUB CLASS="Subscript">
0</SUB>
should be similar for comparable CMOS processes (so, for example, all 0.5 <SPAN CLASS="Symbol">
m</SPAN>
m processes should have approximately the same <SPAN CLASS="Symbol">
t</SPAN>
<SUB CLASS="SubscriptVariable">
c</SUB>
and <SPAN CLASS="EquationNumber">
T</SPAN>
<SUB CLASS="Subscript">
0</SUB>
). The only parameter we can change when using a flip-flop or latch from a cell library is <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
r</SUB>
, and we should allow as much resolution time as we can after the output of a <SPAN CLASS="Emphasis">
latch</SPAN>
before the signal is clocked again. If we use a <SPAN CLASS="Emphasis">
flip-flop </SPAN>
constructed from two latches in series (a master–slave design), then we are sampling the data twice. The resolution time for the first sample <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
r</SUB>
is fixed, it is half the clock cycle (if the clock is high and low for equal times—we say the clock has a 50 percent <A NAME="marker=19104">
</A>
<SPAN CLASS="Definition">
duty cycle</SPAN>
, or equal <A NAME="marker=19105">
</A>
<SPAN CLASS="Definition">
mark–space ratio</SPAN>
). Using such a flip-flop we need to allow as much time as we can before we clock the second sample by connecting two flip-flops in series, without any combinational logic between them, if possible. If you are really in trouble, the next step is to divide the clock so you can extend the resolution time even further.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="3">
<P CLASS="TableTitle">
<A NAME="pgfId=82904">
</A>
TABLE 6.2 <A NAME="22012">
</A>
Metastability parameters for FPGA flip-flops. These figures are not guaranteed by the vendors.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=82910">
</A>
<SPAN CLASS="TableHeads">
FPGA</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=82912">
</A>
<SPAN CLASS="EquationNumber">
T</SPAN>
<SUB CLASS="Subscript">
0</SUB>
<SPAN CLASS="EquationNumber">
/ s</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=82914">
</A>
<SPAN CLASS="Symbol">
t</SPAN>
<SUB CLASS="SubscriptVariable">
c </SUB>
/<SPAN CLASS="TableHeads">
s</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=82916">
</A>
Actel ACT 1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82918">
</A>
1.0E–09</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82920">
</A>
2.17E–10</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=82922">
</A>
Xilinx XC3020-70</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82924">
</A>
1.5E–10</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82926">
</A>
2.71E–10</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=82928">
</A>
QuickLogic QL12x16-0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82930">
</A>
2.94E–11</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82932">
</A>
2.91E–10</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=82934">
</A>
QuickLogic QL12x16-1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82936">
</A>
8.38E–11</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82938">
</A>
2.09E–10</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=82940">
</A>
QuickLogic QL12x16-2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82942">
</A>
1.23E–10</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82944">
</A>
1.85E–10</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=82946">
</A>
Xilinx XC8100</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82948">
</A>
2.15E-12</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82950">
</A>
4.65E–10</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=82952">
</A>
Xilinx XC8100 synchronizer</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82954">
</A>
1.59E-17</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82956">
</A>
2.07E–10</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=82958">
</A>
Altera MAX 7000</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82960">
</A>
2.98E–17</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82962">
</A>
2.00E–10</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=82964">
</A>
Altera FLEX 8000</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82966">
</A>
1.01E–13</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82968">
</A>
7.89E–11</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="3">
<P CLASS="TableLeft">
<A NAME="pgfId=82970">
</A>
Sources: Actel April 1992 data book, p. 5-1, gives C1 = T<SUB CLASS="Subscript">
0</SUB>
= 10<SUP CLASS="Superscript">
–9</SUP>
Hz<SUP CLASS="Superscript">
–1</SUP>
, C2 = 1/<SPAN CLASS="Symbol">
t</SPAN>
<SUB CLASS="SubscriptVariable">
c</SUB>
= 4.6052 ns<SUP CLASS="Superscript">
–1</SUP>
, or <SPAN CLASS="Symbol">
t</SPAN>
<SUB CLASS="SubscriptVariable">
c</SUB>
= 2.17E–10 s and T<SUB CLASS="Subscript">
0</SUB>
= 1.0E–09 s. Xilinx gives K1 = T<SUB CLASS="Subscript">
0</SUB>
= 1.5E–10 s and K2 = 1/<SPAN CLASS="Symbol">
t</SPAN>
<SUB CLASS="SubscriptVariable">
c</SUB>
= 3.69E9 s–1, <SPAN CLASS="Symbol">
t</SPAN>
<SUB CLASS="SubscriptVariable">
c</SUB>
= 2.71E–10 s, for the XC3020-70 (p. 8-20 of 1994 data book). QuickLogic pASIC 1 QL12X16: <SPAN CLASS="Symbol">
t</SPAN>
<SUB CLASS="SubscriptVariable">
c</SUB>
= 0.2 ns to 0.3 ns, T<SUB CLASS="Subscript">
0</SUB>
= 0.3E–10 s to 1.2E–10 s (1994 data book, p. 5-25, Fig. 2). Xilinx XC8100 data, <SPAN CLASS="Symbol">
t</SPAN>
<SUB CLASS="SubscriptVariable">
c</SUB>
= 4.65E–10 s and T<SUB CLASS="Subscript">
0</SUB>
= 2.15E–12 s, is from October 1995 (v. 1.0) data sheet, Fig.17 (the XC8100 was discontinued in August 1996). Altera 1995 data book p. 437, Table 1.</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=77340">
</A>
<A HREF="CH06.4.htm#22012" CLASS="XRef">
Table 6.2</A>
shows flip-flop metastability parameters and <A HREF="CH06.4.htm#29130" CLASS="XRef">
Figure 6.17</A>
graphs the metastability data for <SPAN CLASS="EquationVariables">
f</SPAN>
<SUB CLASS="Subscript">
clock</SUB>
= 10 MHz and <SPAN CLASS="EquationVariables">
f</SPAN>
<SUB CLASS="Subscript">
data</SUB>
= 1 MHz. From this graph we can see the enormous variation in MTBF caused by small variations in <SPAN CLASS="Symbol">
t</SPAN>
<SUB CLASS="SubscriptVariable">
c</SUB>
. For example, in the QuickLogic pASIC 1 series the range of <SPAN CLASS="EquationNumber">
T</SPAN>
<SUB CLASS="Subscript">
0</SUB>
from 0.3 to 1.2 <SPAN CLASS="Symbol">
¥</SPAN>
10<SUP CLASS="Superscript">
–10</SUP>
s is 4:1, but it is the range of <SPAN CLASS="Symbol">
t</SPAN>
<SUB CLASS="SubscriptVariable">
c</SUB>
= 0.2 – 0.3 ns (a variation of only 1:1.5) that is responsible for the enormous variation in MTBF (nearly four orders of magnitude at <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
r</SUB>
= 5 ns). The variation in <SPAN CLASS="Symbol">
t</SPAN>
<SUB CLASS="SubscriptVariable">
c</SUB>
is caused by the variation in <SPAN CLASS="EquationVariables">
GB</SPAN>
between the QuickLogic speed grades. Variation in the other vendors’ parts will be similar, but most vendors do not show this information. To be safe, build a large safety margin for MTBF into any design—it is not unreasonable to use a margin of four orders of magnitude.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=83033">
</A>
</P>
<DIV>
<IMG SRC="CH06-17.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=83036">
</A>
FIGURE 6.17 <A NAME="29130">
</A>
Mean time between failures (MTBF) as a function of resolution time. The data is from FPGA vendors’ data books for a single flip-flop with clock frequency of 10 MHz and a data input frequency of 1 MHz (see <A HREF="CH06.4.htm#22012" CLASS="XRef">
Table 6.2</A>
).</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=19194">
</A>
Some cell libraries include a <SPAN CLASS="Definition">
synchronizer</SPAN>
<A NAME="marker=19198">
</A>
, built from two flip-flops in cascade, that greatly reduces the effective values of <SPAN CLASS="Symbol">
t</SPAN>
<SUB CLASS="SubscriptVariable">
c</SUB>
and <SPAN CLASS="EquationNumber">
T</SPAN>
<SUB CLASS="Subscript">
0</SUB>
over a single flip-flop. The penalty is an extra clock cycle of latency. </P>
<P CLASS="Body">
<A NAME="pgfId=19199">
</A>
To compare discrete TTL parts with ASIC flip-flops, the <A NAME="marker=77435">
</A>
74AS4374 TTL <SPAN CLASS="Definition">
metastable-hardened dual flip-flops</SPAN>
<A NAME="marker=61219">
</A>
, from TI, have <SPAN CLASS="Symbol">
t</SPAN>
<SUB CLASS="SubscriptVariable">
c</SUB>
= 0.42 ns and <SPAN CLASS="EquationNumber">
T</SPAN>
<SUB CLASS="Subscript">
0</SUB>
= 4 ns. The parameter <SPAN CLASS="EquationNumber">
T</SPAN>
<SUB CLASS="Subscript">
0</SUB>
ranges from about 10 s for the <A NAME="marker=77439">
</A>
74LS74 (a regular flip-flop) to 4 ns for the 74AS4374 (over nine orders of magnitude different); <SPAN CLASS="Symbol">
t</SPAN>
<SUB CLASS="SubscriptVariable">
c</SUB>
only varies from 0.42 ns (74AS374) to 1.3 ns (74LS74), but this small variation in <SPAN CLASS="Symbol">
t</SPAN>
<SUB CLASS="SubscriptVariable">
c</SUB>
is just as important. </P>
</DIV>
<HR><P>[ <A HREF="CH06.htm">Chapter start</A> ] [ <A HREF="CH06.3.htm">Previous page</A> ] [ <A HREF="CH06.5.htm">Next page</A> ]</P></BODY>
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