📄 ch06.5.htm
字号:
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML EXPERIMENTAL 970324//EN">
<HTML>
<HEAD>
<META NAME="GENERATOR" CONTENT="Adobe FrameMaker 5.5/HTML Export Filter">
<TITLE> 6.5 Clock Input</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
<DIV>
<P>[ <A HREF="CH06.htm">Chapter start</A> ] [ <A HREF="CH06.4.htm">Previous page</A> ] [ <A HREF="CH06.6.htm">Next page</A> ]</P><!--#include file="AmazonAsic.html"--><HR></DIV>
<H1 CLASS="Heading1">
<A NAME="pgfId=19037">
</A>
6.5 <A NAME="22586">
</A>
Clock Input</H1>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=19044">
</A>
When we bring the clock signal onto a chip, we may need to adjust the logic level (clock signals are often driven by TTL drivers with a high current output capability) and then we need to distribute the clock signal around the chip as it is needed. FPGAs normally provide special clock buffers and clock networks. We need to minimize the clock delay (or latency), but we also need to minimize the clock skew.</P>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=23037">
</A>
6.5.1 Registered Inputs</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=31440">
</A>
Some FPGAs provide a flip-flop or latch that you can use as part of the I/O circuit (registered I/O). For other FPGAs you have to use a flip-flop or latch using the basic logic cell in the core. In either case the important parameter is the input setup time. We can measure the setup with respect to the clock signal at the flip-flop or the clock signal at the clock input pad. The difference between these two parameters is the clock delay.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=31446">
</A>
</P>
<DIV>
<IMG SRC="CH06-18.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=82757">
</A>
FIGURE 6.18 <A NAME="22363">
</A>
Clock input. (a) Timing model with values for a Xilinx XC4005-6. (b) A simplified view of clock distribution. (c) Timing diagram. Xilinx eliminates the variable internal delay <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
PG</SUB>
, by specifying a pin-to-pin setup time, t <SUB CLASS="Subscript">
PSUFmin</SUB>
= 2 ns.</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=31453">
</A>
<A HREF="CH06.5.htm#22363" CLASS="XRef">
Figure 6.18</A>
shows part of the I/O timing model for a Xilinx XC40005-6.<SUP CLASS="Superscript">
<A HREF="#pgfId=32495" CLASS="footnote">
1</A>
</SUP>
</P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=31339">
</A>
<SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
PICK</SUB>
is the fixed setup time for a flip-flop relative to the flip-flop clock.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=31341">
</A>
<SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="Subscript">
skew</SUB>
is the variable <SPAN CLASS="Definition">
clock skew</SPAN>
<A NAME="marker=77646">
</A>
, the signed delay between two clock edges.</LI>
<LI CLASS="BulletLast">
<A NAME="pgfId=31342">
</A>
<SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
PG</SUB>
is the variable clock delay or <SPAN CLASS="Definition">
latency</SPAN>
<A NAME="marker=77645">
</A>
.</LI>
</UL>
<P CLASS="Body">
<A NAME="pgfId=31479">
</A>
To calculate the flip-flop setup time (<SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
PSUFmin</SUB>
) relative to the clock pad (which is the parameter system designers need to know), we subtract the clock delay, so that </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=107344">
</A>
<SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
PSUF</SUB>
= <SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
PICK</SUB>
– <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
PG</SUB>
.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=107347">
</A>
(6.6)</P>
</TD>
</TR>
</TABLE>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=31493">
</A>
<SPAN CLASS="EquationVariables">
</SPAN>
The problem is that we cannot easily calculate <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
PG</SUB>
, since it depends on the clock distribution scheme and where the flip-flop is on the chip. Instead Xilinx specifies <SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
PSUFmin</SUB>
directly, measured from the data pad to the clock pad; this time is called a <SPAN CLASS="Definition">
pin-to-pin timing parameter</SPAN>
<A NAME="marker=32610">
</A>
. Notice <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
PSUF</SUB>
<SUB CLASS="Subscript">
min</SUB>
= 2 ns ≠ <SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
PICK</SUB>
– <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
PG</SUB>
<SUB CLASS="Subscript">
max</SUB>
= –1 ns.</P>
<P CLASS="Body">
<A NAME="pgfId=59975">
</A>
<A HREF="CH06.5.htm#23174" CLASS="XRef">
Figure 6.19</A>
shows that the hold time for a XC4005-6 flip-flop (<SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
CKI</SUB>
) with respect to the flip-flop clock is zero. However, the pin-to-pin hold time including the clock delay is t<SUB CLASS="Subscript">
PHF</SUB>
= 5.5 ns. We can remove this inconvenient hold-time restriction by delaying the input signal. Including a programmable delay allows Xilinx to guarantee the pin-to-pin hold time (<SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
PH</SUB>
) as zero. The penalty is an increase in the pin-to-pin setup time (<SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
PSU</SUB>
) to 21 ns (from 2 ns) for the XC4005-6, for example. </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=59981">
</A>
</P>
<DIV>
<IMG SRC="CH06-19.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=59985">
</A>
FIGURE 6.19 <A NAME="23174">
</A>
Programmable input delay. (a) Pin-to-pin timing model with values from an XC4005-6. (b) Timing diagrams with and without programmable delay.</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=23036">
</A>
We also have to account for clock delay when we register an output. <A HREF="CH06.5.htm#33759" CLASS="XRef">
Figure 6.20</A>
shows the timing model diagram for the clock-to-output delay. </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigTitleSide">
<A NAME="pgfId=32089">
</A>
FIGURE 6.20 <A NAME="33759">
</A>
Registered output. (a) Timing model with values for an XC4005-6 programmed with the fast slew-rate option. (b) Timing diagram.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=32094">
</A>
</P>
<DIV>
<IMG SRC="CH06-20.gif">
</DIV>
</TD>
</TR>
</TABLE>
</DIV>
<HR>
<DIV CLASS="footnotes">
<DIV CLASS="footnote">
<P CLASS="Footnote">
<SPAN CLASS="footnoteNumber">
1.</SPAN>
<A NAME="pgfId=32495">
</A>
The Xilinx XC4005-6 timing parameters are from the 1994 data book p. 2-50 to p. 2-53.</P>
</DIV>
</DIV>
<HR><P>[ <A HREF="CH06.htm">Chapter start</A> ] [ <A HREF="CH06.4.htm">Previous page</A> ] [ <A HREF="CH06.6.htm">Next page</A> ]</P></BODY>
<!--#include file="Copyright.html"--><!--#include file="footer.html"-->
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -