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27-32</P>
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VQFP</P>
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80</P>
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68</P>
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</P>
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PLCC</P>
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44</P>
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52</P>
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44</P>
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PLCC</P>
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68</P>
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45</P>
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28–35</P>
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PLCC</P>
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84</P>
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1.5</P>
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44</P>
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PPGA</P>
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132</P>
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33–34</P>
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Total chip power = 0.2 (N <SPAN CLASS="Symbol">
¥</SPAN>
F1) + 0.085 (M <SPAN CLASS="Symbol">
¥</SPAN>
F2) + 0.8 ( P <SPAN CLASS="Symbol">
¥</SPAN>
F3) mW</P>
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<A NAME="15859">
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(6.7)</P>
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where</P>
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F1 = average logic module switching rate in MHz </P>
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F2 = average clock pin switching rate in MHz </P>
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F3 = average I/O switching rate in MHz </P>
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M = number of logic modules connected to the clock pin </P>
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N = number of logic modules used on the chip </P>
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P = number of I/O pairs used (input + output), with 50 pF load</P>
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As an example of a power-dissipation calculation, consider an Actel 1020B-2 with a 20 MHz clock. We shall initially assume 100 percent utilization of the 547 Logic Modules and assume that each switches at an average speed of 5 MHz. We shall also initially assume that we use all of the 69 I/O Modules and that each switches at an average speed of 5 MHz. Using Eq. <A HREF="CH06.6.htm#15859" CLASS="XRef">
6.7</A>
, the Logic Modules dissipate </P>
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<SPAN CLASS="EquationVariables">
P</SPAN>
<SUB CLASS="SubscriptVariable">
LM</SUB>
= (0.2)(547)(5) = 547 mW ,</P>
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(6.8)</P>
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and the I/O Module dissipation is </P>
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<SPAN CLASS="EquationVariables">
P</SPAN>
<SUB CLASS="SubscriptVariable">
IO</SUB>
= (0.8)(69)(5) = 276 mW .</P>
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(6.9)</P>
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If we assume the clock buffer drives 20 percent of the Logic Modules, then the additional power dissipation due to the clock buffer is </P>
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<SPAN CLASS="EquationVariables">
P</SPAN>
<SUB CLASS="SubscriptVariable">
CLK</SUB>
= (0.085)(547)(0.2)(5) = 46.495 mW .</P>
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(6.10)</P>
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The total power dissipation is thus </P>
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<SPAN CLASS="EquationVariables">
P</SPAN>
<SUB CLASS="SubscriptVariable">
D</SUB>
= (547 + 276 + 46.5) = 869.5 mW ,</P>
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(6.11)</P>
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or about 900 mW (with an accuracy of certainly no better than ± 100 mW). </P>
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Suppose we intend to use a <SPAN CLASS="Definition">
very thin quad flatpack </SPAN>
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</A>
(<SPAN CLASS="Definition">
VQFP</SPAN>
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</A>
<A NAME="marker=78516">
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<A NAME="marker=78517">
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) with no cooling (because we are trying to save area and board height). From <A HREF="CH06.6.htm#34932" CLASS="XRef">
Table 6.3</A>
the thermal resistance, <SPAN CLASS="Symbol">
q</SPAN>
<SUB CLASS="Subscript">
JA</SUB>
, is approximately 68 °CW<SUP CLASS="Superscript">
–1</SUP>
for an 80-pin VQFP. Thus the maximum junction temperature under industrial worst-case conditions (T<SUB CLASS="Subscript">
A</SUB>
= 85 °C) will be </P>
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T<SUB CLASS="Subscript">
J</SUB>
= (85 + (0.87)(68)) = 144.16 °C ,</P>
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(6.12)</P>
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(with an accuracy of no better than 10 °C). Actel specifies the maximum junction temperature for its devices as T<SUB CLASS="Subscript">
Jmax</SUB>
= 150 °C (T<SUB CLASS="Subscript">
Jmax</SUB>
for Altera is also 150 °C, for Xilinx T<SUB CLASS="Subscript">
Jmax</SUB>
= 125°C). Our calculated value is much too close to the rated maximum for comfort; therefore we need to go back and check our assumptions for power dissipation. At or near 100 percent module utilization is not unreasonable for an Actel device, but more questionable is that all nodes and I/Os switch at 5 MHz. </P>
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Our real mistake is trying to use a VQFP package with a high <SPAN CLASS="Symbol">
q</SPAN>
<SUB CLASS="Subscript">
JA</SUB>
for a high-speed design. Suppose we use an 84-pin PLCC package instead. From <A HREF="CH06.6.htm#34932" CLASS="XRef">
Table 6.3</A>
the thermal resistance, <SPAN CLASS="Symbol">
q</SPAN>
<SUB CLASS="Subscript">
JA</SUB>
, for this alternative package is approximately 44 °CW<SUP CLASS="Superscript">
–1</SUP>
. Now the worst-case junction temperature will be a more reasonable </P>
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T<SUB CLASS="Subscript">
J</SUB>
= (85 + (0.87)(44)) = 123.28 °C ,</P>
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(6.13)</P>
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It is possible to estimate the power dissipation of the Actel architecture because the routing is regular and the interconnect capacitance is well controlled (it has to be since we must minimize the number of series antifuses we use). For most other architectures it is much more difficult to estimate power dissipation. The exception, as we saw in Section 5.4 “Altera MAX,” are the programmable ASICs based on programmable logic arrays with passive pull-ups where a substantial part of the power dissipation is static.</P>
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<H2 CLASS="Heading2">
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6.6.2 Power-On Reset</H2>
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Each FPGA has its own power-on reset sequence. For example, a Xilinx FPGA configures all flip-flops (in either the CLBs or IOBs) as either SET or RESET. After chip programming is complete, the global SET/RESET signal forces all flip-flops on the chip to a known state. This is important since it may determine the initial state of a state machine, for example.</P>
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<HR>
<DIV CLASS="footnotes">
<DIV CLASS="footnote">
<P CLASS="Footnote">
<SPAN CLASS="footnoteNumber">
1.</SPAN>
<A NAME="pgfId=85174">
</A>
1994 data book, p.1-9</P>
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<DIV CLASS="footnote">
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<SPAN CLASS="footnoteNumber">
2.</SPAN>
<A NAME="pgfId=84930">
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CPGA = ceramic pin-grid array; CQFP = ceramic quad flatpack; PQFP = plastic quad flatpack; VQFP = very thin quad flatpack; PLCC = plastic leaded chip carrier; PPGA = plastic pin-grid array.</P>
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<DIV CLASS="footnote">
<P CLASS="TableFootnote">
<SPAN CLASS="footnoteNumber">
3.</SPAN>
<A NAME="pgfId=78144">
</A>
<SPAN CLASS="Symbol">
q</SPAN>
<SUB CLASS="Subscript">
JA</SUB>
varies with die size.</P>
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<DIV CLASS="footnote">
<P CLASS="TableFootnote">
<SPAN CLASS="footnoteNumber">
4.</SPAN>
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Data from Actel 1994 data book p. 1-9, p. 1-45, and p. 1-94.</P>
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<DIV CLASS="footnote">
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5.</SPAN>
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Data from Xilinx 1994 data book p. 4-26 and p. 4-27.</P>
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