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<TITLE> 6.7 Xilinx I/O Block</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
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<P>[ <A HREF="CH06.htm">Chapter start</A> ] [ <A HREF="CH06.6.htm">Previous page</A> ] [ <A HREF="CH06.8.htm">Next page</A> ]</P><!--#include file="AmazonAsic.html"--><HR></DIV>
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6.7 <A NAME="25943">
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Xilinx I/O Block</H1>
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The Xilinx I/O cell is the <A NAME="marker=17013">
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<SPAN CLASS="Definition">
input/output block </SPAN>
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IOB</SPAN>
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. <A HREF="CH06.7.htm#26411" CLASS="XRef">
Figure 6.21</A>
shows the Xilinx XC4000 IOB, which is similar to the IOB in the XC2000, XC3000, and XC5200 but performs a superset of the options in these other Xilinx FPGAs. </P>
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FIGURE 6.21 <A NAME="26411">
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The Xilinx XC4000 family IOB (input/output block). (<SPAN CLASS="Emphasis">
Source:</SPAN>
Xilinx.)</P>
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The outputs contain features that allow you to do the following:</P>
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Switch between a totem-pole and a complementary output (XC4000H).</LI>
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Include a passive pull-up or pull-down (both <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel devices) with a typical resistance of about 50 k<SPAN CLASS="Symbol">
W </SPAN>
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Invert the three-state control (output enable OE or three-state, TS).</LI>
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Include a flip-flop, or latch, or a direct connection in the output path.</LI>
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Control the slew rate of the output.</LI>
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The features on the inputs allow you to do the following:</P>
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Configure the input buffer with TTL or CMOS thresholds.</LI>
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Include a flip-flop, or latch, or a direct connection in the input path.</LI>
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Switch in a delay to eliminate an input hold time.</LI>
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FIGURE 6.22 <A NAME="27226">
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The Xilinx LCA (Logic Cell Array) timing model. The paths show different uses of CLBs (Configurable Logic Blocks) and IOBs (Input/Output Blocks). The parameters shown are for an XC5210-6. (Source: Xilinx.)</P>
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<A HREF="CH06.7.htm#27226" CLASS="XRef">
Figure 6.22</A>
shows the timing model for the XC5200 family.<SUP CLASS="Superscript">
<A HREF="#pgfId=32502" CLASS="footnote">
1</A>
</SUP>
It is similar to the timing model for all the other Xilinx LCA FPGAs with one exception—the XC5200 does not have registers in the I/O cell; you go directly to the core CLBs to include a flip-flop or latch on an input or output.</P>
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6.7.1 <A NAME="36311">
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Boundary Scan</H2>
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Testing PCBs can be done using a bed-of-nails tester. This approach becomes very difficult with closer IC pin spacing and more sophisticated assembly methods using surface-mount technology and multilayer boards. The IEEE implemented boundary-scan standard 1149.1 to simplify the problem of testing at the board level. The Joint Test Action Group (JTAG) developed the standard; thus the terms JTAG boundary scan or just JTAG are commonly used.</P>
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Many FPGAs contain a standard boundary-scan test logic structure with a four-pin interface. By using these four signals, you can program the chip using ISP, as well as serially load commands and data into the chips to control the outputs and check the inputs. This is a great improvement over bed-of-nails testing. We shall cover boundary scan in detail in Section 14.6, “Scan Test.”</P>
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1.</SPAN>
<A NAME="pgfId=32502">
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October 1995 (v. 3.0) data sheet.</P>
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