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6.4 (**Bipolar drivers, 60 min.) The circuit in <A HREF="CH06.1.htm#37492" CLASS="XRef">
Figure 6.3</A>
uses <SPAN CLASS="EmphasisPrefix">
npn</SPAN>
transistors. </P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=64963">
</A>
a. Design a similar circuit that uses <SPAN CLASS="EmphasisPrefix">
pnp</SPAN>
transistors. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=64978">
</A>
b. The <SPAN CLASS="EmphasisPrefix">
pnp</SPAN>
circuit may work better, why? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=64965">
</A>
c. Design an even better circuit that uses <SPAN CLASS="EmphasisPrefix">
npn</SPAN>
and <SPAN CLASS="EmphasisPrefix">
pnp</SPAN>
transistors. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=64966">
</A>
d. Explain why your circuit is even better. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=64967">
</A>
e. Draw a diagram for a controller using op-amps instead of bipolar transistors.</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=19588">
</A>
6.5 <A NAME="14076">
</A>
(Xilinx output buffers, 15 min.) For the Xilinx XC2000 and XC3000 series<SUP CLASS="Superscript">
<A HREF="#pgfId=37440" CLASS="footnote">
9</A>
</SUP>
: <SPAN CLASS="EquationNumber">
I</SPAN>
<SUB CLASS="Subscript">
OLpeak</SUB>
= 120 mA and <SPAN CLASS="EquationNumber">
I</SPAN>
<SUB CLASS="Subscript">
OHpeak</SUB>
= 80 mA; for the XC4000 family: <SPAN CLASS="EquationNumber">
I</SPAN>
<SUB CLASS="Subscript">
OLpeak</SUB>
= 160 mA and <SPAN CLASS="EquationNumber">
I</SPAN>
<SUB CLASS="Subscript">
OHpeak</SUB>
= 130 mA; and for the XC7300 series: <SPAN CLASS="EquationNumber">
I</SPAN>
<SUB CLASS="Subscript">
OLpeak</SUB>
= 100 mA and <SPAN CLASS="EquationNumber">
I</SPAN>
<SUB CLASS="Subscript">
OHpeak</SUB>
= 65 mA. For a typical 0.8–1.0 <SPAN CLASS="Symbol">
m</SPAN>
m process:</P>
<P CLASS="ExcerciseList">
<A NAME="pgfId=17820">
</A>
<SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel (20/1): <SPAN CLASS="EquationVariables">
I</SPAN>
<SUB CLASS="SubscriptVariable">
DS</SUB>
= 3.0–5.0 mA with <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DS</SUB>
= –5 V, <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
GS</SUB>
= –5 V</P>
<P CLASS="ExcerciseList">
<A NAME="pgfId=17712">
</A>
<SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel (20/1): <SPAN CLASS="EquationVariables">
I</SPAN>
<SUB CLASS="SubscriptVariable">
DS</SUB>
= 7.5–10.0 mA with <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DS</SUB>
= 5 V, <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
GS</SUB>
= 5 V</P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=55337">
</A>
a. Calculate the effective sizes of the transistors in the Xilinx output buffer. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=55341">
</A>
b. Why might these only be “effective” sizes?</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=55340">
</A>
c. The Xilinx data book gives values for “source current and output high impedance” shown in <A HREF="CH06.a.htm#33610" CLASS="XRef">
Table 6.8</A>
. Graph the buffer characteristics when sourcing current.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=55344">
</A>
d. Explain which parts in <A HREF="CH06.a.htm#33610" CLASS="XRef">
Table 6.8</A>
use complementary output buffers and which use totem-pole outputs and explain how you can tell.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=55345">
</A>
e. Can you explain how Xilinx arrived at the figures for impedance? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=55346">
</A>
f. Comment on the method that Xilinx used.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=55347">
</A>
g. Suggest and calculate a better measure of impedance.</LI>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="5">
<P CLASS="TableTitle">
<A NAME="pgfId=17847">
</A>
TABLE 6.8 <A NAME="33610">
</A>
Xilinx output buffer characteristics.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=80679">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="3">
<P CLASS="TableFirst">
<A NAME="pgfId=80692">
</A>
<SPAN CLASS="TableHeads">
V</SPAN>
<SUB CLASS="Subscript">
O</SUB>
<SPAN CLASS="TableHeads">
</SPAN>
(output voltage)<SUP CLASS="Superscript">
<A HREF="#pgfId=80704" CLASS="footnote">
10</A>
</SUP>
/ V</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=80687">
</A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=17926">
</A>
<SPAN CLASS="TableHeads">
Part</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=17899">
</A>
<SPAN CLASS="TableHeads">
4</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=17901">
</A>
<SPAN CLASS="TableHeads">
3</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=17903">
</A>
<SPAN CLASS="TableHeads">
2</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=17905">
</A>
<SPAN CLASS="TableHeads">
Impedance/</SPAN>
<SPAN CLASS="Symbol">
W</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=18015">
</A>
<SPAN CLASS="TableHeads">
IO (2018)</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=17907">
</A>
–30 </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=17909">
</A>
–52</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=17911">
</A>
–60</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=17913">
</A>
30</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=17995">
</A>
<SPAN CLASS="TableHeads">
IO (3020)</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=17997">
</A>
–35</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=17999">
</A>
–60</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=18001">
</A>
–75</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=18003">
</A>
30</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=18005">
</A>
<SPAN CLASS="TableHeads">
IO (4005)</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=18007">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=18009">
</A>
–12</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=18011">
</A>
–50</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=18013">
</A>
25</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=18023">
</A>
<SPAN CLASS="TableHeads">
IO (73108)</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=17977">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=17979">
</A>
–10</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=17981">
</A>
–26</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=17983">
</A>
40</P>
</TD>
</TR>
</TABLE>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=24407">
</A>
6.6 (Xilinx logic levels, 10 min.) Most manufacturers measure <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
OLmax</SUB>
with <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
set to its minimum value, Xilinx measures <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
OLmax</SUB>
at <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
DDmax</SUB>
. For example, for the Xilinx XC4000<SUP CLASS="Superscript">
<A HREF="#pgfId=84769" CLASS="footnote">
11</A>
</SUP>
: <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
OLmax</SUB>
= 0.4 V at <SPAN CLASS="EquationNumber">
I</SPAN>
<SUB CLASS="Subscript">
OLmax</SUB>
= 12 mA and <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
DDmax</SUB>
. A footnote also explains that <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
OLmax</SUB>
is measured with “50 % of the outputs simultaneously sinking 12 mA.”</P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=55348">
</A>
a. Can you explain why Xilinx measures <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
OLmax</SUB>
this way?</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=55349">
</A>
b. What information do you need to know to estimate <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
OLmax</SUB>
if all the other outputs were <SPAN CLASS="Emphasis">
not</SPAN>
sourcing or sinking any current.</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=19954">
</A>
6.7 (Output levels, 10 min.) In <A HREF="CH06.2.htm#40360" CLASS="XRef">
Figure 6.7</A>
(b–d) the PAD signal is labeled with different levels: In <A HREF="CH06.2.htm#40360" CLASS="XRef">
Figure 6.7</A>
(b) the PAD high and low levels are <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
OHmin</SUB>
and <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
OLmax</SUB>
respectively, in <A HREF="CH06.2.htm#40360" CLASS="XRef">
Figure 6.7</A>
(c) they are <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
and <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
OLmax</SUB>
, and in <A HREF="CH06.2.htm#40360" CLASS="XRef">
Figure 6.7</A>
(c) they are <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
OHmin</SUB>
and <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
SS</SUB>
. </P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=55350">
</A>
a. Explain why this is.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=55351">
</A>
b. In no more than 20 words explain the difference between <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
and <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
OHmin</SUB>
as well as the difference between <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
OLmax</SUB>
and <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
SS</SUB>
.</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=20408">
</A>
6.8 (TTL and CMOS outputs, 10 min.) The ACT 2 figures for <SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
DLH</SUB>
and <SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
DHL</SUB>
in <A HREF="CH06.2.htm#40360" CLASS="XRef">
Figure 6.7</A>
are for the CMOS levels. For TTL levels the figures are (with the CMOS figures in parentheses): <SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
DLH</SUB>
= 10.6 ns (13.5 ns), and <SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
DHL</SUB>
= 13.4 ns (11.2 ns). The output buffer is the same in both cases, but the delays are measured using different levels. Explain the differences in these delays quantitatively.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=20424">
</A>
6.9 (Bus-keeper contention, 30 min.) <A HREF="CH06.a.htm#31981" CLASS="XRef">
Figure 6.25</A>
shows a three-state bus, similar to <A HREF="CH06.2.htm#13063" CLASS="XRef">
Figure 6.5</A>
, that has a bus keeper on CHIP1 and a pull-up resistor that is part of a Xilinx IOB on CHIP2—we have a type of bus-keeper contention. For the XC3000 the <SPAN CLASS="Definition">
pull-up current</SPAN>
<A NAME="marker=20573">
</A>
is 0.02–0.17 mA and thus RL1 is between 5 and 50 k<SPAN CLASS="Symbol">
W</SPAN>
(1994 data book, p. 2-155).</P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=55352">
</A>
a. Explain what might happen when both the bus drivers turn off.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=55355">
</A>
b. Have you considered all possibilities? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=55353">
</A>
c. Is bus-keeper contention a problem?</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=55354">
</A>
d. In the PCI specification control signals are required to be <A NAME="marker=60318">
</A>
sustained three-state. A driver must deassert a control signal to the inactive state (high for the PCI control signals) for at least one clock cycle before three-stating the line. This means that a driver has to “put the signal back where it found it.” Does this affect your answers?</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=55356">
</A>
e. Suggest a “fix” that stops you having to worry about any potential problems.</LI>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigTitleSide">
<A NAME="pgfId=20418">
</A>
FIGURE 6.25 <A NAME="31981">
</A>
A bus keeper, BK1, and pull-up resistor, RL1, on the same bus.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=20423">
</A>
</P>
<DIV>
<IMG SRC="CH06-25.gif">
</DIV>
</TD>
</TR>
</TABLE>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=20425">
</A>
6.10 (Short-circuit, 10 min.) What happens if you short-circuit the output of a complementary output buffer to <SPAN CLASS="Bold">
(a)</SPAN>
GND and <SPAN CLASS="Bold">
(b)</SPAN>
VDD? <SPAN CLASS="Bold">
(c)</SPAN>
What difference does it make if the output buffer is complementary or a totem-pole?</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=27519">
</A>
6.11 (Transmission line bias, 10 min.)</P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=55362">
</A>
a. Why do we adjust the resistors in <A HREF="CH06.2.htm#28845" CLASS="XRef">
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