ch06.a.htm
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2,923 行
<A NAME="pgfId=85319">
</A>
<SPAN CLASS="TableHeadFont">
I/O cell functions</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85321">
</A>
TS, SR, IC/T , JTAG, SCH</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85323">
</A>
TS, SR, 5/3, PCI, 4SRC, 12SNK</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85325">
</A>
TS, SR, PU, OD, IT/C, 16SRC, 16SNK</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85327">
</A>
<SPAN CLASS="TableHeadFont">
Number of I/O cells</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85329">
</A>
91 (20220)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=85330">
</A>
–270 (22000)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85332">
</A>
36 (7032)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=85333">
</A>
–164 (7256)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85335">
</A>
96 (6002)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=85336">
</A>
–160 (6010)</P>
</TD>
</TR>
</TABLE>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="4">
<P CLASS="TableTitle">
<A NAME="pgfId=85357">
</A>
TABLE 6.7 <A NAME="23383">
</A>
Programmable ASIC I/O logic resources (contd.).</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=85365">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=85367">
</A>
<SPAN CLASS="TableHeads">
Actel (ACT 3)</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=85369">
</A>
<SPAN CLASS="TableHeads">
Xilinx LCA (XC5200)</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=85371">
</A>
<SPAN CLASS="TableHeads">
Altera FLEX (8000/10k)</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85373">
</A>
<SPAN CLASS="TableHeads">
I/O cell name</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85375">
</A>
I/O Module</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85377">
</A>
IOB (I/O Block)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85379">
</A>
IOE (I/O Element)</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85387">
</A>
<SPAN CLASS="TableHeads">
I/O cell functions</SPAN>
<SUP CLASS="Superscript">
<A HREF="#pgfId=85386" CLASS="footnote">
5</A>
</SUP>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85392">
</A>
TS, SR, (RIO)<SUP CLASS="Superscript">
<A HREF="#pgfId=85391" CLASS="footnote">
6</A>
</SUP>
, 8SRC, 12SNK</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85394">
</A>
TS, PU, PD, JTAG</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85396">
</A>
TS, SR, RI or RO, JTAG, PCI(8k), 4SRC, 12SNK</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85398">
</A>
<SPAN CLASS="TableHeads">
Number of I/O cells</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85400">
</A>
80 (1415)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=85401">
</A>
–228 (14100)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=85402">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85404">
</A>
84 (5202)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=85405">
</A>
–244 (5215)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=85406">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85408">
</A>
78 (8282)–208 (81500)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=85409">
</A>
150 (10K10)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=85410">
</A>
–406 (10K100)</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85412">
</A>
<SPAN CLASS="TableHeads">
</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85414">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85416">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85418">
</A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=85420">
</A>
<SPAN CLASS="TableHeads">
</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=85422">
</A>
<SPAN CLASS="TableHeads">
AMD MACH 5</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=85424">
</A>
<SPAN CLASS="TableHeads">
Actel 3200DX</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=85426">
</A>
<SPAN CLASS="TableHeads">
Altera MAX (EPM 9000)</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85428">
</A>
<SPAN CLASS="TableHeads">
I/O cell name</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85430">
</A>
I/O Cell</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85432">
</A>
I/O Module</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85434">
</A>
IOE (I/O Element)</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85436">
</A>
<SPAN CLASS="TableHeads">
I/O cell functions</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85438">
</A>
TS, 3.2SRC, 16SNK, PCI</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85440">
</A>
Same as ACT 2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85442">
</A>
TS, SR, 5/3, PCI, JTAG, 4SRC, 8SNK</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85444">
</A>
<SPAN CLASS="TableHeads">
Number of I/O cells</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85446">
</A>
120 (M5-128)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=85447">
</A>
–256 (M5-512)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85449">
</A>
126 (A3265DX)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=85450">
</A>
–292 (A32400DX)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85452">
</A>
168 (9320)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=85453">
</A>
–216 (9560)</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85455">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85457">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85459">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85461">
</A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=85463">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=85468">
</A>
<SPAN CLASS="TableHeads">
Xilinx (XC8100)</SPAN>
<SUP CLASS="Superscript">
<A HREF="#pgfId=85467" CLASS="footnote">
7</A>
</SUP>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=85470">
</A>
<SPAN CLASS="TableHeads">
AT&T ORCA 2C</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=85472">
</A>
<SPAN CLASS="TableHeads">
Xilinx (XC4000)</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85474">
</A>
<SPAN CLASS="TableHeads">
I/O cell name</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85476">
</A>
I/O Cell</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85478">
</A>
PIC (Programmable input/output cells)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85480">
</A>
IOB (I/O Block)</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85482">
</A>
<SPAN CLASS="TableHeads">
I/O cell functions</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85484">
</A>
TS, PU, IT/C (global), JTAG, PCI, 4SRC, 4/24SNK<SUP CLASS="Superscript">
<A HREF="#pgfId=85487" CLASS="footnote">
8</A>
</SUP>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85489">
</A>
TS, IT/C, ID, PU, PD, OD, JTAG, PCI, (6SRC and 12SNK) or (3SRC and 6SNK), SCH</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85491">
</A>
TS, RIO, JTAG, ID, IT/C, OT/C, PU, PD, 4SRC, 12SNK, 24SNK (4000A/H)</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85493">
</A>
<SPAN CLASS="TableHeads">
Number of I/O cells</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85495">
</A>
32 (8100)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=85496">
</A>
–208 (8109)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85498">
</A>
160 (2C04)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=85499">
</A>
–480 (2C40)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85501">
</A>
80 (4003)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=85502">
</A>
–256 (4025)</P>
</TD>
</TR>
</TABLE>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=80510">
</A>
a. The delay from a CMOS-level pad input (trip-point of 0.5) to the D input of the input register plus the flip-flop setup time.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=80513">
</A>
b. The delay (measured from the clock, so include the clock-to-Q delay) through the inverter to the output register plus the setup time.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=80514">
</A>
c. The delay from the output register (measured from the clock edge) to the output pad (trip point of 0.5) with a 50 pF load.</LI>
</UL>
<P CLASS="Exercise">
<A NAME="pgfId=16740">
</A>
In each case give your answers: (i) Using data book symbols (specify which symbols and where in the data books you found them); and (ii) as calculated values, in nanoseconds, using a speed grade that you specify. State and explain very clearly any assumptions that you need to make about the clock to determine the setup times.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=16741">
</A>
6.3 (Clock timing, 30 min.) When we calculate FPGA timing we need to include the time it takes to bring the clock onto the chip. For an FPGA you choose, estimate (worst-case commercial) the delay from the clock pad (0.5 trip-point) to the clock pin of an internal flip-flop</P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=80585">
</A>
a. in terms of data book symbols (specify which and where you found them—<SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
AB</SUB>
on p. 2-32 of the ABC 1994 data book, for example), and</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=80589">
</A>
b. as calculated values in nanoseconds.</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=19577">
</A>
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