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<H1 CLASS="Heading1">
<A NAME="pgfId=4949">
</A>
6.10 <A NAME="32266">
</A>
Problems</H1>
<P CLASS="Exercise">
<A NAME="pgfId=84760">
</A>
* = Difficult, ** = Very difficult, *** = Extremely difficult</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=84758">
</A>
6.1 (I/O resources, 60 min.) Obtain the specifications for the latest version of your choice of FPGA vendor from a data book or online data sheet and complete a table in the same format as Tables <A HREF="CH06.a.htm#30436" CLASS="XRef">
6.6</A>
and <A HREF="CH06.a.htm#23383" CLASS="XRef">
6.7</A>
.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="4">
<P CLASS="TableTitle">
<A NAME="pgfId=84159">
</A>
TABLE 6.5 <A NAME="15005">
</A>
I/O Cell Tables.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=84167">
</A>
<SPAN CLASS="TableHeads">
Programmable ASIC family</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=84169">
</A>
Table</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=84171">
</A>
<SPAN CLASS="TableHeads">
Programmable ASIC family</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=84173">
</A>
Table</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=84175">
</A>
Actel (ACT 1)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=84176">
</A>
Xilinx (XC3000)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=84177">
</A>
Actel (ACT 2)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=84178">
</A>
Altera MAX (EPM 5k)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=84179">
</A>
Xilinx EPLD (XC7200/7300)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=84180">
</A>
QuickLogic (pASIC 1)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=84181">
</A>
Crosspoint (CP20K)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=84182">
</A>
Altera MAX (EPM 7000)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=84183">
</A>
Atmel (AT6000)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=84188">
</A>
<A HREF="CH06.a.htm#30436" CLASS="XRef">
Table 6.6</A>
</P>
<P CLASS="Table">
<A NAME="pgfId=84189">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=84191">
</A>
Actel (ACT 3)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=84192">
</A>
Xilinx LCA (XC5200)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=84193">
</A>
Altera FLEX (8000/10k)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=84194">
</A>
AMD MACH 5</P>
<P CLASS="TableLeft">
<A NAME="pgfId=84195">
</A>
Actel 3200DX</P>
<P CLASS="TableLeft">
<A NAME="pgfId=84196">
</A>
Altera MAX (EPM 9000)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=84197">
</A>
Xilinx (XC8100)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=84198">
</A>
AT&T ORCA (2C)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=84199">
</A>
Xilinx (XC4000)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=84204">
</A>
<A HREF="CH06.a.htm#23383" CLASS="XRef">
Table 6.7</A>
</P>
</TD>
</TR>
</TABLE>
<P CLASS="ExerciseHead">
<A NAME="pgfId=16739">
</A>
6.2 (I/O timing, 60 min.) On-chip delays are only half the battle in a typical design. Using data book parameters for an FPGA that you choose, estimate (worst-case commercial) how long it takes to bring a signal on-chip; through an input register (a flip-flop); through a combinational function (assume an inverter); and back off chip again through another (flip-flop) register. Give your answer in three parts: </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="4">
<P CLASS="TableTitle">
<A NAME="pgfId=85190">
</A>
TABLE 6.6 <A NAME="30436">
</A>
Programmable ASIC I/O logic resources.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=85198">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=85200">
</A>
<SPAN CLASS="TableHeads">
Actel (ACT 1)</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=85202">
</A>
<SPAN CLASS="TableHeads">
Xilinx (XC3000)</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=85204">
</A>
<SPAN CLASS="TableHeads">
Actel (ACT 2)</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85206">
</A>
<SPAN CLASS="TableHeads">
I/O cell name</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85208">
</A>
I/O module</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85210">
</A>
IOB (Input/Output Block)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85212">
</A>
I/O module</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85220">
</A>
<SPAN CLASS="TableHeads">
I/O cell functions</SPAN>
<SUP CLASS="Superscript">
<A HREF="#pgfId=85219" CLASS="footnote">
1</A>
</SUP>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85222">
</A>
TS, 10SRC, 10SNK</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85224">
</A>
TS, RIO, IT/C, PU, 4SRC, 4SNK, 8SRC (3100), 8SNK (3100)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85229">
</A>
TS, (RIO)<SUP CLASS="Superscript">
<A HREF="#pgfId=85228" CLASS="footnote">
2</A>
</SUP>
, 10SRC, 10SNK</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85231">
</A>
<SPAN CLASS="TableHeads">
Number of I/O cells</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85233">
</A>
Max. I/O:</P>
<P CLASS="TableLeft">
<A NAME="pgfId=85234">
</A>
57 (1010)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=85235">
</A>
69 (1020)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85237">
</A>
Max. I/O:</P>
<P CLASS="TableLeft">
<A NAME="pgfId=85238">
</A>
64 (3020)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=85239">
</A>
144 (3090)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85241">
</A>
Max. I/O:</P>
<P CLASS="TableLeft">
<A NAME="pgfId=85242">
</A>
83 (1225)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=85243">
</A>
140 (1280)</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85245">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=85247">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=85249">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=85251">
</A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=85253">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=85255">
</A>
<SPAN CLASS="TableHeads">
Altera MAX 5000</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=85257">
</A>
<SPAN CLASS="TableHeads">
Xilinx EPLD</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=85259">
</A>
<SPAN CLASS="TableHeads">
QuickLogic (pASIC 1)</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85261">
</A>
<SPAN CLASS="TableHeads">
I/O cell name</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85263">
</A>
I/O control block</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85265">
</A>
I/O block </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85267">
</A>
Bidirectional input/output cell & dedicated input cell</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85269">
</A>
<SPAN CLASS="TableHeads">
I/O cell functions</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85271">
</A>
TS, 4SRC, 8SNK</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85276">
</A>
(TS), (RI)<SUP CLASS="Superscript">
<A HREF="#pgfId=85275" CLASS="footnote">
3</A>
</SUP>
, 5/3, 4SRC, 12SNK</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85278">
</A>
TS</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85280">
</A>
<SPAN CLASS="TableHeads">
Number of I/O cells </SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85282">
</A>
8 (5016)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=85283">
</A>
–64 (5192)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85285">
</A>
38 (7336)–156 (73144)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=85286">
</A>
36 (7236)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=85287">
</A>
–72 (7272)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85292">
</A>
32 (QL6X8)<SUP CLASS="Superscript">
<A HREF="#pgfId=85291" CLASS="footnote">
4</A>
</SUP>
</P>
<P CLASS="TableLeft">
<A NAME="pgfId=85293">
</A>
–104 (QL16X24)</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85295">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85297">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85299">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85301">
</A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=85303">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=85305">
</A>
<SPAN CLASS="TableHeads">
Crosspoint (CP20K)</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=85307">
</A>
<SPAN CLASS="TableHeads">
Altera MAX 7000</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=85309">
</A>
<SPAN CLASS="TableHeads">
Atmel (AT6000)</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85311">
</A>
<SPAN CLASS="TableHeadFont">
I/O cell name</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85313">
</A>
I/O cell</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85315">
</A>
IOC (I/O Control Block)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=85317">
</A>
Entrance and exit cells</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
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