ch06.2.htm

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Ground bounce may also cause problems at chip inputs. Suppose the inverter M2/M3 is set to have a TTL threshold of 1.4 V and the input, IN1, is at a fixed voltage equal to 3 V (a respectable logic high for bipolar TTL). In this case a ground bounce of greater than 1.6 V will cause the input, IN1, to see a logic low instead of a high and a glitch will be generated on the inverter output, I1. Supply bounce can also occur on the VDD net, but this is usually less severe because the pull-up transistors in an output buffer are usually weaker than the pull-down transistors. The risk of generating a glitch is also greater at the low logic level for TTL-threshold inputs and TTL-level outputs because the low-level noise margins are smaller than the high-level noise margins in TTL.</P>
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Sixteen SSOs, with each output driving 150 pF on a bus, can generate a ground bounce of 1.5 V or more. We cannot simulate this problem easily with FPGAs because we are not normally given the characteristics of the output devices. As a rule of thumb we wish to keep ground bounce below 1 V. To help do this we can limit the maximum number of SSOs, and we can limit the number of I/O buffers that share GND and VDD pads.</P>
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To further reduce the problem, FPGAs now provide options to limit the current flowing in the output buffers, reducing the slew rate and slowing them down. Some FPGAs also have quiet I/O circuits that sense when the input to an output buffer changes. The quiet I/O then starts to change the output using small transistors; shortly afterwards the large output transistors &#8220;drop-in.&#8221; As the output approaches its final value, the large transistors &#8220;kick-out,&#8221; reducing the supply bounce.</P>
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6.2.2&nbsp;Transmission Lines</H2>
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Most of the problems with driving large capacitive loads at high speed occur on a bus, and in this case we may have to consider the bus as a transmission line. <A HREF="CH06.2.htm#30533" CLASS="XRef">
Figure&nbsp;6.9</A>
(a) shows how a transmission line appears to a driver, D1, and receiver, R1, as a constant impedance, the <SPAN CLASS="Definition">
characteristic impedance</SPAN>
<A NAME="marker=34382">
 </A>
 of the line, <SPAN CLASS="EquationVariables">
Z</SPAN>
<SUB CLASS="Subscript">
0</SUB>
. For a typical PCB trace, <SPAN CLASS="EquationVariables">
Z</SPAN>
<SUB CLASS="Subscript">
0</SUB>
 is between 50 <SPAN CLASS="Symbol">
W</SPAN>
 and 100 <SPAN CLASS="Symbol">
W</SPAN>
 .</P>
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FIGURE&nbsp;6.9&nbsp;<A NAME="30533">
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Transmission lines. (a)&nbsp;A printed-circuit board (PCB) trace is a transmission (TX) line. (b)&nbsp;A driver launches an incident wave, which is reflected at the end of the line. (c)&nbsp;A connection starts to look like a transmission line when the signal rise time is about equal to twice the line delay (2<SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
f</SUB>
).</P>
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The voltages on a transmission line are determined by the value of the driver source resistance, <SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="Subscript">
0</SUB>
, and the way that we terminate the end of the transmission line. In <A HREF="CH06.2.htm#30533" CLASS="XRef">
Figure&nbsp;6.9</A>
(a) the termination is just the capacitance of the receiver, <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
in</SUB>
. As the driver switches between 5 V and 0 V, it launches a voltage wave down the line, as shown in <A HREF="CH06.2.htm#30533" CLASS="XRef">
Figure&nbsp;6.9</A>
(b). The wave will be <SPAN CLASS="EquationVariables">
Z</SPAN>
<SUB CLASS="Subscript">
0</SUB>
 / (<SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="Subscript">
0</SUB>
 + <SPAN CLASS="EquationVariables">
Z</SPAN>
<SUB CLASS="Subscript">
0</SUB>
) times 5 V in magnitude, so that if <SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="Subscript">
0</SUB>
 is equal to <SPAN CLASS="EquationVariables">
Z</SPAN>
<SUB CLASS="Subscript">
0</SUB>
, the wave will be 2.5 V.</P>
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Notice that it does not matter what is at the far end of the line. The bus driver sees only <SPAN CLASS="EquationVariables">
Z</SPAN>
<SUB CLASS="Subscript">
0</SUB>
 and not <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
in</SUB>
. Imagine the transmission line as a tunnel; all the bus driver can see at the entrance is a little way into the tunnel&#8212;it could be 500 m or 5 km long. To find out, we have to go with the wave to the end, turn around, come back, and tell the bus driver. The final result will be the same whether the transmission line is there or not, but with a transmission line it takes a little longer for the voltages and currents to settle down. This is rather like the difference between having a conversation by telephone or by post.</P>
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The propagation delay (or <A NAME="marker=27363">
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time of flight), <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
f</SUB>
, for a typical PCB trace is approximately 1 ns for every 15 cm of trace (the signal velocity is about one-half the speed of light). A voltage wave launched on a transmission line takes a time <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
f</SUB>
 to get to the end of the line, where it finds the load capacitance, <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
in</SUB>
. Since no current can flow at this point, there must be a reflection that exactly cancels the incident wave so that the voltage at the input to the receiver, at <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="Subscript">
2</SUB>
, becomes exactly zero at time <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
f</SUB>
. The reflected wave travels back down the line and finally causes the voltage at the output of the driver, at <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="Subscript">
1</SUB>
, to be exactly zero at time 2<SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
f</SUB>
. In practice the nonidealities of the driver and the line cause the waves to have finite rise times. We start to see transmission line behavior if the rise time of the driver is less than 2<SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
f</SUB>
, as shown in <A HREF="CH06.2.htm#30533" CLASS="XRef">
Figure&nbsp;6.9</A>
(c).</P>
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There are several ways to terminate a transmission line. <A HREF="CH06.2.htm#28845" CLASS="XRef">
Figure&nbsp;6.10</A>
 illustrates the following methods:</P>
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<SPAN CLASS="Emphasis">
Open-circuit or capacitive termination.</SPAN>
 The bus termination is the input capacitance of the receivers (usually less than 20 pF). The PCI bus uses this method.</LI>
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<SPAN CLASS="Emphasis">
Parallel resistive termination.</SPAN>
 This requires substantial DC current (5 V / 100 <SPAN CLASS="Symbol">
W</SPAN>
 = 50 mA for a 100 <SPAN CLASS="Symbol">
W</SPAN>
 line). It is used by bipolar logic, for example emitter-coupled logic (ECL), where we typically do not care how much power we use.</LI>
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<SPAN CLASS="Emphasis">
Th&eacute;venin termination. </SPAN>
Connecting 300 <SPAN CLASS="Symbol">
W</SPAN>
 in parallel with 150 <SPAN CLASS="Symbol">
W</SPAN>
 across a 5 V supply is equivalent to a 100 <SPAN CLASS="Symbol">
W</SPAN>
 termination connected to a 1.6 V source. This reduces the DC current drain on the drivers but adds a resistance directly across the supply.</LI>
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<SPAN CLASS="Emphasis">
Series termination at the source.</SPAN>
 Adding a resistor in series with the driver so that the sum of the driver source resistance (which is usually 50 <SPAN CLASS="Symbol">
W</SPAN>
 or even less) and the termination resistor matches the line impedance (usually around 100 <SPAN CLASS="Symbol">
W</SPAN>
). The disadvantage is that it generates reflections that may be close to the switching threshold.</LI>
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<SPAN CLASS="Emphasis">
Parallel termination with a voltage bias.</SPAN>
 This is awkward because it requires a third supply and is normally used only for a specialized high-speed bus.</LI>
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<SPAN CLASS="Emphasis">
Parallel termination with a series capacitance. </SPAN>
This removes the requirement for DC current but introduces other problems. </LI>
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FIGURE&nbsp;6.10&nbsp;<A NAME="28845">
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Transmission line termination. (a)&nbsp;Open-circuit or capacitive termination. (b)&nbsp;Parallel resistive termination. (c)&nbsp;Th&eacute;venin termination. (d)&nbsp;Series termination at the source. (e)&nbsp;Parallel termination using a voltage bias. (f)&nbsp;Parallel termination with a series capacitor.</P>
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Until recently most bus protocols required strong bipolar or BiCMOS output buffers capable of driving all the way between logic levels. The PCI standard uses weaker CMOS drivers that rely on reflection from the end of the bus to allow the intermediate receivers to see the full logic value. Many FPGA vendors now offer complete PCI functions that the ASIC designer can &#8220;drop in&#8221; to an FPGA <A NAME="[PCI, 1995]">
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[PCI, 1995].</P>
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An alternative to using a transmission line that operates across the full swing of the supply voltage is to use current-mode signaling or differential signals with low-voltage swings. These and other techniques are used in specialized bus structures and in high-speed DRAM. Examples are <A NAME="marker=80957">
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Rambus, and <A NAME="marker=80958">
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<SPAN CLASS="Definition">
Gunning transistor logic</SPAN>
 (<A NAME="marker=80959">
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<SPAN CLASS="Definition">
GTL</SPAN>
<A NAME="marker=80960">
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). These are analog rather than digital circuits, but ASIC methods apply if the interface circuits are available as cells, hiding some of the complexity from the designer. For example, Rambus offers a <A NAME="marker=80961">
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<SPAN CLASS="Definition">
Rambus access cell</SPAN>
 (<A NAME="marker=80962">
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<SPAN CLASS="Definition">
RAC</SPAN>
<A NAME="marker=80963">
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) for standard-cell design (but not yet for an FPGA). Directions to more information on these topics are in the bibliography at the end of this chapter.</P>
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<DIV CLASS="footnotes">
<DIV CLASS="footnote">
<P CLASS="Footnote">
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1.</SPAN>
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1994 data book, p.&nbsp;2-159.</P>
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2.</SPAN>
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Application Note XAPP 024.000, Additional XC3000 Data, 1994 data book p.&nbsp;8-15. </P>
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