ch06.2.htm
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t</SPAN>
<SUB CLASS="Subscript">
active</SUB>
. Once the buffer is active, the output transistors turn on, conducting a current <SPAN CLASS="EquationVariables">
I</SPAN>
<SUB CLASS="Subscript">
peak</SUB>
. The output voltage <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
O</SUB>
across the load capacitance, <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
BUS</SUB>
, will <SPAN CLASS="Definition">
slew</SPAN>
<A NAME="marker=66449">
</A>
or change at a steady rate, d<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
O</SUB>
/ d<SPAN CLASS="EquationVariables">
t</SPAN>
= <SPAN CLASS="EquationVariables">
I</SPAN>
<SUB CLASS="Subscript">
peak</SUB>
<SUB CLASS="SubscriptVariable">
</SUB>
/ <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
BUS</SUB>
; thus <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="Subscript">
slew</SUB>
= <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
BUS</SUB>
<SPAN CLASS="Symbol">
D</SPAN>
<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
O</SUB>
/ <SPAN CLASS="EquationVariables">
I</SPAN>
<SUB CLASS="Subscript">
peak</SUB>
, where <SPAN CLASS="Symbol">
D</SPAN>
<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
O</SUB>
is the change in output voltage. </P>
<P CLASS="Body">
<A NAME="pgfId=71892">
</A>
Vendors do not always provide enough information to calculate <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="Subscript">
active</SUB>
and <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="Subscript">
slew</SUB>
separately, but we can usually estimate their sum. Xilinx specifies the time from the three-state input switching to the time the “pad is active and valid” for an XC3000-125 switching with a 50 pF load, to be <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="Subscript">
active</SUB>
= t<SUB CLASS="Subscript">
TSON</SUB>
= 11 ns (fast option), and 27 ns (slew-rate limited option).<SUP CLASS="Superscript">
<A HREF="#pgfId=71802" CLASS="footnote">
1</A>
</SUP>
If we need to drive the bus in less than one clock cycle (30 ns), we will definitely need to use the fast option. </P>
<P CLASS="Body">
<A NAME="pgfId=80946">
</A>
A supplement to the XC3000 timing data specifies the additional fall delay for switching large capacitive loads (above 50 pF) as R<SUB CLASS="Subscript">
fall</SUB>
= 0.06 nspF <SUP CLASS="Superscript">
–1</SUP>
(falling) and R<SUB CLASS="Subscript">
rise</SUB>
= 0.12 nspF<SUP CLASS="Superscript">
–1</SUP>
(rising) using the fast output option.<SUP CLASS="Superscript">
<A HREF="#pgfId=80949" CLASS="footnote">
2</A>
</SUP>
We can thus estimate that</P>
<P CLASS="EquationAlign">
<A NAME="pgfId=80950">
</A>
<SPAN CLASS="EquationVariables">
I</SPAN>
<SUB CLASS="Subscript">
peak</SUB>
<SPAN CLASS="Symbol">
ª</SPAN>
(5 V)/(–0.06 <SPAN CLASS="Symbol">
¥</SPAN>
10<SUP CLASS="Superscript">
3</SUP>
sF <SUP CLASS="Superscript">
–1</SUP>
) <SPAN CLASS="Symbol">
ª</SPAN>
–84 mA (falling) </P>
<P CLASS="EquationAlign">
<A NAME="pgfId=80951">
</A>
and <SPAN CLASS="EquationVariables">
I</SPAN>
<SUB CLASS="Subscript">
peak</SUB>
<SPAN CLASS="Symbol">
ª</SPAN>
(5 V)/(0.12 <SPAN CLASS="Symbol">
¥</SPAN>
10<SUP CLASS="Superscript">
3</SUP>
sF <SUP CLASS="Superscript">
–1</SUP>
) <SPAN CLASS="Symbol">
ª</SPAN>
42 mA (rising). </P>
<P CLASS="Body">
<A NAME="pgfId=96028">
</A>
Now we can calculate,</P>
<P CLASS="Equation">
<A NAME="pgfId=96030">
</A>
<SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="Subscript">
slew</SUB>
= R<SUB CLASS="Subscript">
fall</SUB>
<SPAN CLASS="EquationNumber">
(</SPAN>
<SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
BUS</SUB>
– 50 pF) = (90 pF – 50 pF) (0.06 nspF <SUP CLASS="Superscript">
–1</SUP>
) or 2.4 ns ,</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=96031">
</A>
for a total falling delay of 11 + 2.4 = 13.4 ns. The rising delay is slower at 11 + (40 pF)(0.12 nspF <SUP CLASS="Superscript">
–1</SUP>
) or 15.8 ns. This leaves (30 – 15.8) ns, or about 14 ns worst-case, to generate the output enable signal CHIP2.OE (t<SUB CLASS="Subscript">
3OE </SUB>
in <A HREF="CH06.2.htm#13207" CLASS="XRef">
Figure 6.6</A>
) and still leave time <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="Subscript">
spare</SUB>
before the bus data is latched on the next clock edge. We can thus probably use a XC3000 part for a 30 MHz bus transceiver, but only if we use the fast slew-rate option.</P>
<P CLASS="Body">
<A NAME="pgfId=71907">
</A>
An aside: Our example looks a little like the PCI bus used on Pentium and PowerPC systems, but the bus transactions are simplified. PCI buses use a <SPAN CLASS="Definition">
sustained three-state</SPAN>
<A NAME="marker=71908">
</A>
system (<A NAME="marker=71909">
</A>
<SPAN CLASS="Definition">
s / t / s</SPAN>
<A NAME="marker=71910">
</A>
). On the PCI bus an s / t / s driver must drive the bus high for at least one clock cycle before letting it float. A new driver may not start driving the bus until a clock edge after the previous driver floats it. After such a <SPAN CLASS="Definition">
turnaround cycle</SPAN>
<A NAME="marker=71911">
</A>
a new driver will always find the bus parked high.</P>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=23046">
</A>
6.2.1 Supply Bounce</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=73809">
</A>
<A HREF="CH06.2.htm#25606" CLASS="XRef">
Figure 6.8</A>
(a) shows an <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor, M1, that is part of an output buffer driving an output pad, OUT1; M2 and M3 form an inverter connected to an input pad, IN1; and M4 and M5 are part of another output buffer connected to an output pad, OUT2. As M1 sinks current pulling OUT1 low (<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
o</SUB>
<SUB CLASS="Subscript">
1</SUB>
in <A HREF="CH06.2.htm#25606" CLASS="XRef">
Figure 6.8</A>
b), a substantial current <SPAN CLASS="EquationVariables">
I</SPAN>
<SUB CLASS="SubscriptVariable">
OL</SUB>
may flow in the resistance, <SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
S</SUB>
, and inductance, <SPAN CLASS="EquationVariables">
L</SPAN>
<SUB CLASS="SubscriptVariable">
S</SUB>
, that are between the on-chip GND net and the off-chip, external ground connection.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=73821">
</A>
</P>
<DIV>
<IMG SRC="CH06-8.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=73825">
</A>
FIGURE 6.8 <A NAME="25606">
</A>
Supply bounce. (a) As the pull-down device, M1, switches, it causes the GND net (value <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
SS</SUB>
) to bounce. (b) The supply bounce is dependent on the output slew rate. (c) Ground bounce can cause other output buffers to generate a logic glitch. (d) Bounce can also cause errors on other inputs.</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=23097">
</A>
The voltage drop across <SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
S</SUB>
and <SPAN CLASS="EquationVariables">
L</SPAN>
<SUB CLASS="SubscriptVariable">
S</SUB>
causes a spike (or <A NAME="marker=24029">
</A>
transient) on the GND net, changing the value of <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
SS</SUB>
, leading to a problem known as <SPAN CLASS="Definition">
supply bounce</SPAN>
<A NAME="marker=23952">
</A>
. The situation is illustrated in <A HREF="CH06.2.htm#25606" CLASS="XRef">
Figure 6.8</A>
(a), with <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
SS</SUB>
bouncing to a maximum of <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
OLP</SUB>
. This <SPAN CLASS="Definition">
ground bounce</SPAN>
<A NAME="marker=23951">
</A>
causes the voltage at the output, <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
o</SUB>
<SUB CLASS="Subscript">
2</SUB>
, to bounce also. If the threshold of the gate that OUT2 is driving is a TTL level at 1.4 V, for example, a ground bounce of more than 1.4 V will cause a logic high <SPAN CLASS="Definition">
glitch</SPAN>
<A NAME="marker=23958">
</A>
(a momentary transition from one logic level to the opposite logic level and back again).</P>
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