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<TITLE> 6.2 AC Output</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
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6.2 <A NAME="32781">
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AC Output</H1>
<P CLASS="BodyAfterHead">
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<A HREF="CH06.2.htm#13063" CLASS="XRef">
Figure 6.5</A>
shows an example of an off-chip three-state bus. Chips that have inputs and outputs connected to a bus are called <SPAN CLASS="Definition">
bus transceivers</SPAN>
<A NAME="marker=59202">
</A>
. Can we use FPGAs to perform the role of bus transceivers? We will focus on one bit, B1, on bus BUSA, and we shall call it BUSA.B1. We need unique names to refer to signals on each chip; thus CHIP1.OE means the signal OE inside CHIP1. Notice that CHIP1.OE is not connected to CHIP2.OE.</P>
<TABLE>
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<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=66185">
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<DIV>
<IMG SRC="CH06-5.gif">
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</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=66188">
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FIGURE 6.5 <A NAME="13063">
</A>
A three-state bus. (a) Bus parasitic capacitance. (b) The output buffers in each chip. The ASIC CHIP1 contains a bus keeper, BK1.</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=59746">
</A>
<A HREF="CH06.2.htm#13207" CLASS="XRef">
Figure 6.6</A>
shows the timing of part of a <SPAN CLASS="Definition">
bus transaction</SPAN>
<A NAME="marker=20333">
</A>
(a sequence of signals on a bus): </P>
<OL>
<LI CLASS="NumberFirst">
<A NAME="pgfId=20224">
</A>
Initially CHIP2 drives BUSA.B1 high (CHIP2.D1 is '1' and CHIP2.OE is '1').</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=20225">
</A>
The buffer output enable on CHIP2 (CHIP2.OE) goes low, <SPAN CLASS="Definition">
floating</SPAN>
<A NAME="marker=66346">
</A>
the bus. The bus will stay high because we have a bus keeper, BK1. </LI>
<LI CLASS="NumberList">
<A NAME="pgfId=20229">
</A>
The buffer output enable on CHIP3 (CHIP3.OE) goes high and the buffer drives a low onto the bus (CHIP3.D1 is '0').</LI>
</OL>
<P CLASS="Body">
<A NAME="pgfId=66059">
</A>
We wish to calculate the delays involved in driving the off-chip bus in <A HREF="CH06.2.htm#13207" CLASS="XRef">
Figure 6.6</A>
. In order to find <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="Subscript">
float</SUB>
, we need to understand how Actel specifies the delays for its I/O cells. <A HREF="CH06.2.htm#40360" CLASS="XRef">
Figure 6.7</A>
(a) shows the circuit used for measuring I/O delays for the ACT FPGAs. These measurements do not use the same trip points that are used to characterize the internal logic (Actel uses input and output trip points of 0.5 for internal logic delays).</P>
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<P CLASS="TableFigTitleSide">
<A NAME="pgfId=66069">
</A>
FIGURE 6.6 <A NAME="13207">
</A>
Three-state bus timing for <A HREF="CH06.2.htm#13063" CLASS="XRef">
Figure 6.5</A>
. The on-chip delays, <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="Subscript">
2OE</SUB>
and<SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="Subscript">
3OE</SUB>
, for the logic that generates signals CHIP2.E1 and CHIP3.E1 are derived from the timing models described in Chapter <A HREF="/Humuhumu/from Antibes/Prof.htm#22465" CLASS="XRef">
5</A>
(the minimum values for each chip would be the clock-to-Q delay times). </P>
</TD>
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<P CLASS="TableFigure">
<A NAME="pgfId=66074">
</A>
</P>
<DIV>
<IMG SRC="CH06-6.gif">
</DIV>
</TD>
</TR>
</TABLE>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=59823">
</A>
</P>
<DIV>
<IMG SRC="CH06-7.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=59826">
</A>
FIGURE 6.7 <A NAME="40360">
</A>
(a) The test circuit for characterizing the ACT 2 and ACT 3 I/O delay parameters. (b) Output buffer propagation delays from the data input to PAD (output enable, E, is high). (c) Three-state delay with D low. (d) Three-state delay with D high. Delays are shown for ACT 2 'Std' speed grade, worst-case commercial conditions (<SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
L</SUB>
= 1 k<SPAN CLASS="Symbol">
W</SPAN>
, <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
L</SUB>
= 50 pF, V<SUB CLASS="Subscript">
OHmin</SUB>
= 2.4 V, V<SUB CLASS="Subscript">
OLmax</SUB>
= 0.5 V). (The Actel three-state buffer is named TRIBUFF, an input buffer INBUF, and the output buffer, OUTBUF.)</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=64792">
</A>
Notice in <A HREF="CH06.2.htm#40360" CLASS="XRef">
Figure 6.7</A>
(a) that when the output enable E is '0' the output is <SPAN CLASS="Definition">
three-stated</SPAN>
<A NAME="marker=71985">
</A>
(<SPAN CLASS="Definition">
high-impedance</SPAN>
<A NAME="marker=71987">
</A>
or <A NAME="marker=71986">
</A>
<SPAN CLASS="Definition">
hi-Z</SPAN>
). Different companies use different polarity and naming conventions for the “output enable” signal on a three-state buffer. To measure the buffer delay (measured from the change in the enable signal, E) Actel uses a resistor load (<SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
L</SUB>
= 1 k<SPAN CLASS="Symbol">
W</SPAN>
for ACT 2). The resistor pulls the buffer output high or low depending on whether we are measuring:</P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=64793">
</A>
<SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
ENZL</SUB>
, when the output switches from hi-Z to '0'.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=64794">
</A>
<SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
ENLZ</SUB>
, when the output switches from '0' to hi-Z.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=19326">
</A>
<SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
ENZH</SUB>
, when the output switches from hi-Z to '1'.</LI>
<LI CLASS="BulletLast">
<A NAME="pgfId=19327">
</A>
<SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
ENHZ</SUB>
, when the output switches from '1' to hi-Z.</LI>
</UL>
<P CLASS="Body">
<A NAME="pgfId=21240">
</A>
Other vendors specify the <SPAN CLASS="Definition">
time to float</SPAN>
<A NAME="marker=66322">
</A>
a three-state output buffer directly (t<SUB CLASS="Subscript">
fr</SUB>
and t<SUB CLASS="Subscript">
ff</SUB>
in <A HREF="CH06.2.htm#40360" CLASS="XRef">
Figure 6.7</A>
c and d). This delay time has different names (and definitions): <SPAN CLASS="Definition">
disable time</SPAN>
<A NAME="marker=23080">
</A>
, <SPAN CLASS="Definition">
time to begin hi-Z</SPAN>
<A NAME="marker=23073">
</A>
, or <SPAN CLASS="Definition">
time to turn off</SPAN>
<A NAME="marker=23075">
</A>
. </P>
<P CLASS="Body">
<A NAME="pgfId=80976">
</A>
Actel does not specify the time to float but, since <SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
L</SUB>
<SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
L</SUB>
= 50 ns, we know <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
RC</SUB>
= –<SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
L</SUB>
<SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
L</SUB>
ln 0.9 or approximately 5.3 ns. Now we can estimate that</P>
<P CLASS="Equation">
<A NAME="pgfId=66347">
</A>
t<SUB CLASS="Subscript">
fr</SUB>
= t<SUB CLASS="Subscript">
ENLZ</SUB>
– <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
RC</SUB>
= 11.1 – 5.3 = 5.8 ns, and t<SUB CLASS="Subscript">
ff</SUB>
= 9.4 – 5.3 = 4.1 ns, </P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=66349">
</A>
and thus the Actel buffer can float the bus in <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="Subscript">
float</SUB>
= 4.1 ns (<A HREF="CH06.2.htm#13207" CLASS="XRef">
Figure 6.6</A>
).</P>
<P CLASS="Body">
<A NAME="pgfId=20861">
</A>
The Xilinx FPGA is responsible for the second part of the bus transaction. The time to make the buffer CHIP2.B1 active is <SPAN CLASS="EquationVariables">
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