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<TITLE> 6.3 DC Input </TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
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<H1 CLASS="Heading1">
<A NAME="pgfId=80970">
</A>
6.3 <A NAME="31122">
</A>
DC Input </H1>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=26931">
</A>
Suppose we have a pushbutton switch connected to the input of an FPGA as shown in <A HREF="CH06.3.htm#17973" CLASS="XRef">
Figure 6.11</A>
(a). Most FPGA input pads are directly connected to a buffer. We need to ensure that the input of this buffer never floats to a voltage between valid logic levels (which could cause both <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel and <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistors in the buffer to turn on, leading to oscillation or excessive power dissipation) and so we use the optional pull-up resistor (usually about 100 k<SPAN CLASS="Symbol">
W</SPAN>
) that is available on many FPGAs (we could also connect a 1 k<SPAN CLASS="Symbol">
W</SPAN>
pull-up or pull-down resistor externally).</P>
<P CLASS="Body">
<A NAME="pgfId=27430">
</A>
Contacts may bounce as a switch is operated (<A HREF="CH06.3.htm#17973" CLASS="XRef">
Figure 6.11</A>
b). In the case of a Xilinx XC4000 the effective pull-up resistance is 5–50 k<SPAN CLASS="Symbol">
W</SPAN>
(since the specified pull-up current is between 0.2 and 2.0 mA) and forms an <SPAN CLASS="Emphasis">
RC</SPAN>
time constant with the parasitic capacitance of the input pad and the external circuit. This time constant (typically hundreds of nanoseconds) will normally be much less than the time over which the contacts bounce (typically many milliseconds). The buffer output may thus be a series of pulses extending for several milliseconds. It is up to you to deal with this in your logic. For example, you may want to <SPAN CLASS="Definition">
debounce</SPAN>
<A NAME="marker=27502">
</A>
the waveform in <A HREF="CH06.3.htm#17973" CLASS="XRef">
Figure 6.11</A>
(b) using an SR flip-flop.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigTitleSide">
<A NAME="pgfId=49472">
</A>
FIGURE 6.11 <A NAME="17973">
</A>
A switch input. (a) A pushbutton switch connected to an input buffer with a pull-up resistor. (b) As the switch bounces several pulses may be generated.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=26939">
</A>
</P>
<DIV>
<IMG SRC="CH06-11.gif">
</DIV>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=23110">
</A>
A bouncing switch may create a noisy waveform in the time domain, we may also have noise in the voltage level of our input signal. The <SPAN CLASS="Definition">
Schmitt-trigger</SPAN>
<A NAME="marker=26870">
</A>
inverter in <A HREF="CH06.3.htm#20622" CLASS="XRef">
Figure 6.12</A>
(a) has a lower switching threshold of 2 V and an upper switching threshold of 3 V. The difference between these thresholds is the <SPAN CLASS="Definition">
hysteresis</SPAN>
<A NAME="marker=26873">
</A>
, equal to 1 V in this case. If we apply the noisy waveform shown in <A HREF="CH06.3.htm#20622" CLASS="XRef">
Figure 6.12</A>
(b) to an inverter with no hysteresis, there will be a glitch at the output, as shown in <A HREF="CH06.3.htm#20622" CLASS="XRef">
Figure 6.12</A>
(c). As long as the noise on the waveform does not exceed the hysteresis, the Schmitt-trigger inverter will produce the glitch-free output of <A HREF="CH06.3.htm#20622" CLASS="XRef">
Figure 6.12</A>
(d). </P>
<P CLASS="Body">
<A NAME="pgfId=27439">
</A>
Most FPGA input buffers have a small hysteresis (the 200 mV that Xilinx uses is a typical figure) centered around 1.4 V (for compatibility with TTL), as shown in <A HREF="CH06.3.htm#20622" CLASS="XRef">
Figure 6.12</A>
(e). Notice that the drawing inside the symbol for a Schmitt trigger looks like the transfer characteristic for a buffer, but is backward for an inverter. Hysteresis in the input buffer also helps prevent oscillation and noise problems with inputs that have slow rise times, though most FPGA manufacturers still have a restriction that input signals must have a rise time faster than several hundred nanoseconds.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=26779">
</A>
</P>
<DIV>
<IMG SRC="CH06-12.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=26781">
</A>
FIGURE 6.12 <A NAME="20622">
</A>
DC input. (a) A Schmitt-trigger inverter. (b) A noisy input signal. (c) Output from an inverter with no hysteresis. (d) Hysteresis helps prevent glitches. (e) A typical FPGA input buffer with a hysteresis of 200 mV centered around a threshold of 1.4 V.</P>
</TD>
</TR>
</TABLE>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=19020">
</A>
6.3.1 Noise Margins</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=84836">
</A>
<A HREF="CH06.3.htm#16772" CLASS="XRef">
Figure 6.13</A>
(a) and (b) show the worst-case DC transfer characteristics of a CMOS inverter. <A HREF="CH06.3.htm#16772" CLASS="XRef">
Figure 6.13</A>
(a) shows a situation in which the process and device sizes create the lowest possible switching threshold. We define the maximum voltage that will be recognized as a '0' as the point at which the gain (<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="Subscript">
out</SUB>
/ <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="Subscript">
in</SUB>
) of the inverter is –1. This point is <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
ILmax</SUB>
= 1V in the example shown in <A HREF="CH06.3.htm#16772" CLASS="XRef">
Figure 6.13</A>
(a). This means that any input voltage that is lower than 1V will definitely be recognized as a '0', even with the most unfavorable inverter characteristics. At the other worst-case extreme we define the minimum voltage that will be recognized as a '1' as <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
IHmin</SUB>
= 3.5V (for the example in <A HREF="CH06.3.htm#16772" CLASS="XRef">
Figure 6.13</A>
b). </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=84854">
</A>
</P>
<DIV>
<IMG SRC="CH06-13.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=84858">
</A>
FIGURE 6.13 <A NAME="16772">
</A>
Noise margins. (a) Transfer characteristics of a CMOS inverter with the lowest switching threshold. (b) The highest switching threshold. (c) A graphical representation of CMOS logic thresholds. (d) Logic thresholds at the inputs and outputs of a logic gate or an ASIC. (e) The switching thresholds viewed as a plug and socket. (f) CMOS plugs fit CMOS sockets and the clearances are the noise margins.</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=27898">
</A>
<A HREF="CH06.3.htm#16772" CLASS="XRef">
Figure 6.13</A>
(c) depicts the following relationships between the various voltage levels at the inputs and outputs of a logic gate:</P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=27899">
</A>
A logic '1' output must be between <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
OHmin</SUB>
and <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=27900">
</A>
A logic '0' output must be between <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
SS</SUB>
and <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
OLmax</SUB>
.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=27901">
</A>
A logic '1' input must be above the <SPAN CLASS="Definition">
high-level input voltage</SPAN>
<A NAME="marker=74869">
</A>
, V<SUB CLASS="Subscript">
IHmin</SUB>
.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=27902">
</A>
A logic '0' input must be below the <SPAN CLASS="Definition">
low-level input voltage</SPAN>
<A NAME="marker=74870">
</A>
, V<SUB CLASS="Subscript">
ILmax</SUB>
.</LI>
<LI CLASS="BulletLast">
<A NAME="pgfId=74874">
</A>
Clamp diodes prevent an input exceeding <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
or going lower than <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
SS</SUB>
.</LI>
</UL>
<P CLASS="Body">
<A NAME="pgfId=79345">
</A>
The voltages, <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
OHmin</SUB>
, <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
OLmax</SUB>
, <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
IHmin</SUB>
, and <SPAN CLASS="EquationNumber">
V</SPAN>
<A NAME="marker=79344">
</A>
<SUB CLASS="Subscript">
ILmax</SUB>
, are the <SPAN CLASS="Definition">
logic thresholds</SPAN>
for a technology. A logic signal outside the areas bounded by these logic thresholds is “bad”—an unrecognizable logic level in an electronic no-man’s land. <A HREF="CH06.3.htm#16772" CLASS="XRef">
Figure 6.13</A>
(d) shows typical logic thresholds for a CMOS-compatible FPGA. The <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
IHmin</SUB>
and <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
ILmax</SUB>
logic thresholds come from measurements in <A HREF="CH06.3.htm#16772" CLASS="XRef">
Figure 6.13</A>
(a) and (b) and <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
OHmin</SUB>
and <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
OLmax</SUB>
come from the measurements shown in <A HREF="CH06.1.htm#22612" CLASS="XRef">
Figure 6.2</A>
(c). </P>
<P CLASS="Body">
<A NAME="pgfId=80977">
</A>
<A HREF="CH06.3.htm#16772" CLASS="XRef">
Figure 6.13</A>
(d) illustrates how logic thresholds form a plug and socket for any gate, group of gates, or even a chip. If a plug fits a socket, we can connect the two components together and they will have compatible logic levels. For example, <A HREF="CH06.3.htm#16772" CLASS="XRef">
Figure 6.13</A>
(e) shows that we can connect two CMOS gates or chips together.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=79380">
</A>
</P>
<DIV>
<IMG SRC="CH06-14.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=79383">
</A>
FIGURE 6.14 <A NAME="37860">
</A>
TTL and CMOS logic thresholds. (a) TTL logic thresholds. (b) Typical CMOS logic thresholds. (c) A TTL plug will not fit in a CMOS socket. (d) Raising V<SUB CLASS="Subscript">
OHmin</SUB>
solves the problem.</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=79370">
</A>
<A HREF="CH06.3.htm#16772" CLASS="XRef">
Figure 6.13</A>
(f) shows that we can even add some noise that shifts the input levels and the plug will still fit into the socket. In fact, we can shift the plug down by exactly <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
OHmin</SUB>
– <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
IHmin</SUB>
(4.5 – 3.5 = 1 V) and still maintain a valid '1'. We can shift the plug up by <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
ILmax</SUB>
– <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
OLmax</SUB>
(1.0 – 0.5 = 0.5 V) and still maintain a valid '0'. These clearances between plug and socket are the <SPAN CLASS="Definition">
noise margins</SPAN>
<A NAME="marker=79371">
</A>
: </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=104080">
</A>
<SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
NMH</SUB>
= <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
OHmin</SUB>
– <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
IHmin</SUB>
<SPAN CLASS="EquationNumber">
</SPAN>
and <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
NML</SUB>
= <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
ILmax</SUB>
– <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
OLmax</SUB>
.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=104083">
</A>
<A NAME="10713">
</A>
(6.1)</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=27913">
</A>
<SPAN CLASS="EquationNumber">
</SPAN>
For two logic systems to be compatible, the plug must fit the socket. This requires both the <SPAN CLASS="Definition">
high-level noise margin</SPAN>
<A NAME="marker=77166">
</A>
(V<SUB CLASS="Subscript">
NMH</SUB>
) and the <SPAN CLASS="Definition">
low-level noise margin</SPAN>
<A NAME="marker=77167">
</A>
(V<SUB CLASS="Subscript">
NML</SUB>
) to be positive. We also want both noise margins to be as large as possible to give us maximum immunity from noise and other problems at an interface.</P>
<P CLASS="Body">
<A NAME="pgfId=97866">
</A>
<A HREF="CH06.3.htm#37860" CLASS="XRef">
Figure 6.14</A>
(a) and (b) show the logic thresholds for TTL together with typical CMOS logic thresholds. <A HREF="CH06.3.htm#37860" CLASS="XRef">
Figure 6.14</A>
(c) shows the problem with trying to plug a TTL chip into a CMOS input level—the lowest permissible TTL output level, <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
OHmin</SUB>
= 2.7 V, is too low to be recognized as a logic '1' by the CMOS input. This is fixed by most FPGA manufacturers by raising <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
OHmin</SUB>
<SPAN CLASS="EquationNumber">
</SPAN>
to around 3.8–4.0 V (<A HREF="CH06.3.htm#37860" CLASS="XRef">
Figure 6.14</A>
d). <A HREF="CH06.3.htm#21725" CLASS="XRef">
Table 6.1</A>
lists the logic thresholds for several FPGAs.</P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=27893">
</A>
6.3.2 Mixed-Voltage Systems</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=30950">
</A>
To reduce power consumption and allow CMOS logic to be scaled below 0.5 <SPAN CLASS="Symbol">
m</SPAN>
m it is necessary to reduce the power supply voltage below 5 V. The <A NAME="marker=32590">
</A>
JEDEC 8 [<A NAME="JEDEC I/O">
</A>
JEDEC I/O] series of standards sets the next lower supply voltage as 3.3 ± 0.3 V. <A HREF="CH06.3.htm#38960" CLASS="XRef">
Figure 6.15</A>
(a) and (b) shows that the 3 V CMOS I/O logic-thresholds can be made compatible with 5 V systems. Some FPGAs can operate on both 3 V and 5 V supplies, typically using one voltage for internal (or core) logic, <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="Subscript">
DDint</SUB>
<SPAN CLASS="EquationNumber">
</SPAN>
and another for the I/O circuits, <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="Subscript">
DDI/O</SUB>
(<A HREF="CH06.3.htm#38960" CLASS="XRef">
Figure 6.15</A>
c). </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="13">
<P CLASS="TableTitle">
<A NAME="pgfId=78915">
</A>
TABLE 6.1 <A NAME="21725">
</A>
FPGA logic thresholds.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=78941">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="TableFirst">
<A NAME="pgfId=78943">
</A>
<SPAN CLASS="TableHeads">
I/O options</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="TableFirst">
<A NAME="pgfId=78947">
</A>
<SPAN CLASS="TableHeads">
Input levels</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="4">
<P CLASS="TableFirst">
<A NAME="pgfId=78951">
</A>
<SPAN CLASS="TableHeads">
Output levels (high current)</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="4">
<P CLASS="TableFirst">
<A NAME="pgfId=78959">
</A>
<SPAN CLASS="TableHeads">
Output levels (low current)</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=78967">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=78969">
</A>
<SPAN CLASS="TableHeads">
Input</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=78971">
</A>
<SPAN CLASS="TableHeads">
Output</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=78973">
</A>
<SPAN CLASS="TableHeads">
V</SPAN>
<SUB CLASS="Subscript">
IH</SUB>
</P>
<P CLASS="TableFirst">
<A NAME="pgfId=78974">
</A>
<SPAN CLASS="TableHeads">
(min)</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=78976">
</A>
<SPAN CLASS="TableHeads">
V</SPAN>
<SUB CLASS="Subscript">
IL</SUB>
</P>
<P CLASS="TableFirst">
<A NAME="pgfId=78977">
</A>
(max)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=78979">
</A>
<SPAN CLASS="TableHeads">
V</SPAN>
<SUB CLASS="Subscript">
OH</SUB>
</P>
<P CLASS="TableFirst">
<A NAME="pgfId=78980">
</A>
(min)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
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