ch07.1.htm
来自「介绍asci设计的一本书」· HTM 代码 · 共 2,844 行 · 第 1/5 页
HTM
2,844 行
m</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=9854">
</A>
25 tracks = 170 <SPAN CLASS="Symbol">
m</SPAN>
m</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=12442">
</A>
Channel area per LM (X <SPAN CLASS="Symbol">
¥</SPAN>
Y2)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=12444">
</A>
43,050 <SPAN CLASS="Symbol">
m</SPAN>
m<SUP CLASS="Superscript">
2</SUP>
= 43 k <SPAN CLASS="Symbol">
l</SPAN>
<SUP CLASS="Superscript">
2</SUP>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=12516">
</A>
15,300 <SPAN CLASS="Symbol">
m</SPAN>
m<SUP CLASS="Superscript">
2</SUP>
= 43 k <SPAN CLASS="Symbol">
l</SPAN>
<SUP CLASS="Superscript">
2</SUP>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=12452">
</A>
LM and routing area (X <SPAN CLASS="Symbol">
¥</SPAN>
Y1 + X <SPAN CLASS="Symbol">
¥</SPAN>
Y2)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=12454">
</A>
70,000 <SPAN CLASS="Symbol">
m</SPAN>
m<SUP CLASS="Superscript">
2</SUP>
= 70 k <SPAN CLASS="Symbol">
l</SPAN>
<SUP CLASS="Superscript">
2</SUP>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=12456">
</A>
25,000 <SPAN CLASS="Symbol">
m</SPAN>
m<SUP CLASS="Superscript">
2</SUP>
= 70 k <SPAN CLASS="Symbol">
l</SPAN>
<SUP CLASS="Superscript">
2</SUP>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=9856">
</A>
Antifuse capacitance</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=9858">
</A>
—</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=9860">
</A>
10 fF</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=26676">
</A>
Metal capacitance</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=26678">
</A>
0.2 pFmm<SUP CLASS="Superscript">
–1</SUP>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=26680">
</A>
0.2 pFmm<SUP CLASS="Superscript">
–1</SUP>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=9868">
</A>
Output stub length</P>
<P CLASS="TableLeft">
<A NAME="pgfId=26693">
</A>
(spans 3 LMs + 4 channels)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=9870">
</A>
4 channels = 1688<SPAN CLASS="Symbol">
m</SPAN>
m</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=9872">
</A>
4 channels = 1012 <SPAN CLASS="Symbol">
m</SPAN>
m</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=26638">
</A>
Output stub metal capacitance</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=26640">
</A>
0.34 pF</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=26642">
</A>
0.20 pF</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=26632">
</A>
Output stub antifuse connections</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=26634">
</A>
100</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=26636">
</A>
100</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=26652">
</A>
Output stub antifuse capacitance</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=26654">
</A>
—</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=26656">
</A>
1.0 pF</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=9928">
</A>
Horiz. track length</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=9930">
</A>
4–44 cols. = 600–6600 <SPAN CLASS="Symbol">
m</SPAN>
m</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=9932">
</A>
4–44 cols. = 360–3960 <SPAN CLASS="Symbol">
m</SPAN>
m</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=9934">
</A>
Horiz. track metal capacitance</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=9936">
</A>
0.1–1.3 pF</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=9938">
</A>
0.07–0.8 pF</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=9940">
</A>
Horiz. track antifuse connections</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=9942">
</A>
52–572 antifuses</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=9944">
</A>
52–572 antifuses</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=9946">
</A>
Horiz. track antifuse capacitance</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=9948">
</A>
—</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=9950">
</A>
0.52–5.72 pF</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=9952">
</A>
Long vertical track (LVT)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=9954">
</A>
8–14 channels = 3760–6580 <SPAN CLASS="Symbol">
m</SPAN>
m</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=9956">
</A>
8–14 channels = 2240–3920 <SPAN CLASS="Symbol">
m</SPAN>
m</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=11377">
</A>
LVT metal capacitance</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=11379">
</A>
0.08–0.13 pF</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=11381">
</A>
0.45–0.8 pF</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=9970">
</A>
LVT track antifuse connections</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=9972">
</A>
200–350 antifuses</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=9974">
</A>
200–350 antifuses</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=9976">
</A>
LVT track antifuse capacitance</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=9978">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=9980">
</A>
2–3.5 pF</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=11693">
</A>
Antifuse resistance (ACT 1)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=11695">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=11697">
</A>
0.5 k <SPAN CLASS="Symbol">
W</SPAN>
(typ.), 0.7 k <SPAN CLASS="Symbol">
W</SPAN>
(max.)</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=11440">
</A>
We can use the figures from <A HREF="CH07.1.htm#28701" CLASS="XRef">
Table 7.2</A>
to estimate the interconnect delays. First we calculate the following resistance and capacitance values:</P>
<OL>
<LI CLASS="NumberFirst">
<A NAME="pgfId=26586">
</A>
The antifuse resistance is assumed to be <SPAN CLASS="EquationVariables">
R</SPAN>
= 0.5 k<SPAN CLASS="Symbol">
W</SPAN>
.</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=26603">
</A>
<SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
0</SUB>
= 1.2 pF is the sum of the gate output capacitance (which we shall neglect) and the output stub capacitance (1.0 pF due to antifuses, 0.2 pF due to metal). The contribution from this term is zero in our calculation because we have neglected the pull resistance of the driving gate.</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=26615">
</A>
<SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
1</SUB>
= <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
3</SUB>
= 0.59 pF (0.52 pF due to antifuses, 0.07 pF due to metal) corresponding to a minimum-length horizontal track.</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=26619">
</A>
<SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
2</SUB>
= 4.3 pF (3.5 pF due to antifuses, 0.8 pF due to metal) corresponding to a LVT in a 1020B.</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=26589">
</A>
The estimated input capacitance of a gate is <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
4</SUB>
= 0.02 pF (the exact value will depend on which input of a Logic Module we connect to).</LI>
</OL>
<P CLASS="Body">
<A NAME="pgfId=26590">
</A>
From Eq. <A HREF="CH07.1.htm#36693" CLASS="XRef">
7.7</A>
, the Elmore time constant for a four-antifuse connection is </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnRight">
<A NAME="pgfId=47399">
</A>
<SPAN CLASS="Symbol">
t</SPAN>
<SUB CLASS="SubscriptVariable">
D</SUB>
<SUB CLASS="Subscript">
4</SUB>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=47401">
</A>
=</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnLeft">
<A NAME="pgfId=47403">
</A>
4(0.5)(0.02) + 3(0.5)(0.59) + 2(0.5)(4.3) + (0.5)(0.59) </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=47405">
</A>
(7.8)</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnRight">
<A NAME="pgfId=47424">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=47426">
</A>
=</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnLeft">
<A NAME="pgfId=47428">
</A>
5.52 ns .</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqn">
<A NAME="pgfId=47430">
</A>
</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=11466">
</A>
This matches delays obtained from the Actel delay calculator. For example, an LVT adds between 5–10 ns delay in an ACT 1 FPGA (6–12 ns for ACT 2, and 4–14 ns for ACT 3). The LVT connection is about the slowest connection that we can make in an ACT array. Normally less than 10 percent of all connections need to use an LVT and we see why Actel takes great care to make sure that this is the case.</P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=9789">
</A>
7.1.5 ACT 2 and ACT 3 Interconnect</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=1531">
</A>
The ACT 1 architecture uses two antifuses for routing nearby modules, three antifuses to join horizontal segments, and four antifuses to use a horizontal or vertical long track. The ACT 2 and ACT 3 architectures use increased interconnect resources over the ACT 1 device that we have described. This reduces further the number of connections that need more than two antifuses. Delay is also reduced by decreasing the population of antifuses in the channels, and by decreasing the antifuse resistance of certain critical antifuses (by increasing the programming current).</P>
<P CLASS="Body">
<A NAME="pgfId=11812">
</A>
The <A NAME="marker=1543">
</A>
channel density is the absolute minimum number of tracks needed in a channel to make a given set of connections (see <A HREF="/Humuhumu/from Antibes/Prof.htm#32630" CLASS="XRef">
Section 17.2.2, “Measurement of Channel Density”</A>
). Software to route connections using channeled routing is so efficient that, given complete freedom in location of wires, a channel router can usually complete the connections with the number of tracks equal or close to the theoretical minimum, the channel density. Actel’s studies on segmented channel routing have shown that increasing the number of horizontal tracks slightly (by approximately 10 percent) above density can lead to very high routing completion rates. </P>
<P CLASS="Body">
<A NAME="pgfId=26754">
</A>
The ACT 2 devices have 36 horizontal tracks per channel rather than the 22 available in the ACT 1 architecture. Horizontal track segments in an ACT 3 device range from a module pair to the full channel length. Vertical tracks are: input (with a two channel span: one up, one down); output (with a four-channel span: two up, two down); and long (LVT). Four LVTs are shared by each column pair. The ACT 2/3 Logic Modules can accept five inputs, rather than four inputs for the ACT 1 modules, and thus the ACT 2/3 Logic Modules need an extra two vertical tracks per channel. The number of tracks per column thus increases from 13 to 15 in the ACT 2/3 architecture. </P>
<P CLASS="Body">
<A NAME="pgfId=1557">
</A>
The greatest challenge facing the Actel FPGA architects is the resistance of the polysilicon-diffusion antifuse. The nominal antifuse resistance in the ACT 1–2 1–2 <SPAN CLASS="Symbol">
m</SPAN>
m processes (with a 5 mA programming current) is approximately 500 <SPAN CLASS="Symbol">
W</SPAN>
and, in the worst case, may be as high as 700 <SPAN CLASS="Symbol">
W </SPAN>
. The high resistance severely limits the number of antifuses in a connection. The ACT 2/3 devices assign a special antifuse to each output allowing a direct connection to an LVT. This reduces the number of antifuses in a connection using an LVT to three. This type of antifuse (a <A NAME="ma⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?