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<TITLE> 7.1 Actel ACT</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
<DIV>
<P>[ <A HREF="CH07.htm">Chapter start</A> ] [ <A HREF="CH07.htm">Previous page</A> ] [ <A HREF="CH07.2.htm">Next page</A> ]</P><!--#include file="AmazonAsic.html"--><HR></DIV>
<H1 CLASS="Heading1">
<A NAME="pgfId=1300">
</A>
7.1 <A NAME="17885">
</A>
Actel ACT</H1>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=24341">
</A>
The Actel ACT family interconnect scheme shown in <A HREF="CH07.1.htm#34174" CLASS="XRef">
Figure 7.1</A>
is similar to a channeled gate array. The channel routing uses dedicated rectangular areas of fixed size within the chip called <A NAME="marker=24342">
</A>
<SPAN CLASS="Definition">
wiring channels</SPAN>
(or just <A NAME="marker=24343">
</A>
<SPAN CLASS="Definition">
channels</SPAN>
). The <A NAME="marker=24344">
</A>
<SPAN CLASS="Definition">
horizontal channels</SPAN>
run across the chip in the horizontal direction. In the vertical direction there are similar <A NAME="marker=24345">
</A>
<SPAN CLASS="Definition">
vertical channels</SPAN>
that run over the top of the basic logic cells, the Logic Modules. Within the horizontal or vertical channels wires run horizontally or vertically, respectively, within <A NAME="marker=24346">
</A>
<SPAN CLASS="Definition">
tracks</SPAN>
. Each track holds one wire. The <A NAME="marker=24347">
</A>
<SPAN CLASS="Definition">
capacity</SPAN>
of a fixed wiring channel is equal to the number of tracks it contains. <A HREF="CH07.1.htm#38982" CLASS="XRef">
Figure 7.2</A>
shows a detailed view of the channel and the connections to each Logic Module—the <SPAN CLASS="Definition">
input stubs</SPAN>
<A NAME="marker=24352">
</A>
and <SPAN CLASS="Definition">
output stubs</SPAN>
<A NAME="marker=24353">
</A>
. </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=24362">
</A>
</P>
<DIV>
<IMG SRC="CH07-1.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=24366">
</A>
FIGURE 7.1 <A NAME="39257">
</A>
The interconnect architecture used in an Actel ACT family FPGA. (<SPAN CLASS="Emphasis">
Source:</SPAN>
Actel.)</P>
</TD>
</TR>
</TABLE>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=24372">
</A>
</P>
<DIV>
<IMG SRC="CH07-2.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=24376">
</A>
FIGURE 7.2 <A NAME="23536">
</A>
<A NAME="38982">
</A>
ACT 1 horizontal and vertical channel architecture. (Source: Actel.)</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=9061">
</A>
In a channeled gate array the designer decides the location and length of the interconnect within a channel. In an FPGA the interconnect is fixed at the time of manufacture. To allow programming of the interconnect, Actel divides the fixed interconnect wires within each channel into various lengths or <A NAME="marker=9062">
</A>
wire segments. We call this <A NAME="marker=9063">
</A>
segmented channel routing, a variation on channel routing. Antifuses join the wire segments. The designer then programs the interconnections by blowing antifuses and making connections between wire segments; unwanted connections are left unprogrammed. A statistical analysis of many different layouts determines the optimum number and the lengths of the wire segments.</P>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=1351">
</A>
7.1.1 Routing Resources</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=1355">
</A>
The ACT 1 interconnection architecture uses 22 horizontal tracks per channel for signal routing with three tracks dedicated to VDD, GND, and the global clock (GCLK), making a total of 25 tracks per channel. Horizontal segments vary in length from four columns of Logic Modules to the entire row of modules (Actel calls these long segments <A NAME="marker=1353">
</A>
<SPAN CLASS="Definition">
long lines</SPAN>
). </P>
<P CLASS="Body">
<A NAME="pgfId=1363">
</A>
Four Logic Module inputs are available to the channel below the Logic Module and four inputs to the channel above the Logic Module. Thus eight vertical tracks per Logic Module are available for inputs (four from the Logic Module above the channel and four from the Logic Module below). These connections are the <A NAME="marker=1361">
</A>
input stubs.</P>
<P CLASS="Body">
<A NAME="pgfId=2734">
</A>
The single Logic Module output connects to a vertical track that extends across the two channels above the module and across the two channels below the module. This is the <A NAME="marker=2735">
</A>
output stub. Thus module outputs use four vertical tracks per module (counting two tracks from the modules below, and two tracks from the modules above each channel). One vertical track per column is a <A NAME="marker=2736">
</A>
long vertical track (<A NAME="marker=27407">
</A>
LVT<A NAME="marker=27406">
</A>
) that spans the entire height of the chip (the 1020 contains some segmented LVTs). There are thus a total of 13 vertical tracks per column in the ACT 1 architecture (eight for inputs, four for outputs, and one for an LVT).</P>
<P CLASS="Body">
<A NAME="pgfId=6143">
</A>
<A HREF="CH07.1.htm#30876" CLASS="XRef">
Table 7.1</A>
shows the routing resources for both the ACT 1 and ACT 2 families. The last two columns show the total number of antifuses (including antifuses in the I/O cells) on each chip and the total number of antifuses assuming the wiring channels are <A NAME="marker=11434">
</A>
fully populated with antifuses (an antifuse at every horizontal and vertical interconnect intersection). The ACT 1 devices are very nearly fully populated. </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="7">
<P CLASS="TableTitle">
<A NAME="pgfId=6349">
</A>
TABLE 7.1 <A NAME="34174">
</A>
<A NAME="30876">
</A>
Actel FPGA routing resources.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=6146">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=6148">
</A>
<SPAN CLASS="TableHeads">
Horizontal tracks per channel, H</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=6150">
</A>
<SPAN CLASS="TableHeads">
Vertical tracks per column, V</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=6152">
</A>
<SPAN CLASS="TableHeads">
Rows, R</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=6154">
</A>
<SPAN CLASS="TableHeads">
Columns, C</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=6281">
</A>
<SPAN CLASS="TableHeads">
Total</SPAN>
</P>
<P CLASS="TableFirst">
<A NAME="pgfId=11899">
</A>
<SPAN CLASS="TableHeads">
antifuses</SPAN>
</P>
<P CLASS="TableFirst">
<A NAME="pgfId=27417">
</A>
on each chip</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=6283">
</A>
<SPAN CLASS="TableHeads">
H</SPAN>
<SPAN CLASS="Symbol">
¥</SPAN>
<SPAN CLASS="TableHeads">
V</SPAN>
<SPAN CLASS="Symbol">
¥</SPAN>
<SPAN CLASS="TableHeads">
R</SPAN>
<SPAN CLASS="TableHeads">
</SPAN>
<SPAN CLASS="Symbol">
¥</SPAN>
<SPAN CLASS="TableHeads">
C</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6156">
</A>
<SPAN CLASS="TableHeads">
A1010</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6158">
</A>
22</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6160">
</A>
13</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6162">
</A>
8</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6164">
</A>
44</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6285">
</A>
112,000</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6287">
</A>
100,672</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6166">
</A>
<SPAN CLASS="TableHeads">
A1020</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6207">
</A>
22</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6209">
</A>
13</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6172">
</A>
14</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6174">
</A>
44</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6289">
</A>
186,000</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6291">
</A>
176,176</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6231">
</A>
<SPAN CLASS="TableHeads">
A1225A</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6233">
</A>
36</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6235">
</A>
15</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6237">
</A>
13</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6239">
</A>
46</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6293">
</A>
250,000</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6295">
</A>
322,920</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6241">
</A>
<SPAN CLASS="TableHeads">
A1240A</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6243">
</A>
36</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6245">
</A>
15</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6247">
</A>
14</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6249">
</A>
62</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6297">
</A>
400,000</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6299">
</A>
468,720</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6251">
</A>
<SPAN CLASS="TableHeads">
A1280A</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6253">
</A>
36</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6255">
</A>
15</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6257">
</A>
18</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6259">
</A>
82</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6301">
</A>
750,000</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6303">
</A>
797,040</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=2740">
</A>
If the Logic Module at the end of a net is less than two rows away from the driver module, a connection requires two antifuses, a vertical track, and two horizontal segments. If the modules are more than two rows apart, a connection between them will require a long vertical track together with another vertical track (the output stub) and two horizontal tracks. To connect these tracks will require a total of four antifuses in series and this will add delay due to the resistance of the antifuses. To examine the extent of this delay problem we need some help from the analysis of RC networks.</P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=10558">
</A>
7.1.2 <A NAME="38826">
</A>
Elmore’s Constant</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=27464">
</A>
<A HREF="CH07.1.htm#27071" CLASS="XRef">
Figure 7.3</A>
shows an <A NAME="marker=27452">
</A>
<SPAN CLASS="Definition">
RC tree</SPAN>
—representing a net with a <SPAN CLASS="Definition">
fanout</SPAN>
<A NAME="marker=27453">
</A>
of two. We shall assume that all nodes are initially charged to <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="Subscript">
DD</SUB>
= 1 V, and that we short node 0 to ground, so <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="Subscript">
0</SUB>
= 0 V, at time <SPAN CLASS="EquationVariables">
t</SPAN>
= 0 sec. We need to find the node voltages, <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="Subscript">
1</SUB>
to <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="Subscript">
4</SUB>
, as a function of time. A similar problem arose in the design of wideband vacuum tube distributed amplifiers in the 1940s. <A NAME="marker=27465">
</A>
Elmore found a measure of delay that we can use today [<A NAME="Rubenstein83">
</A>
Rubenstein, Penfield, and Horowitz, 1983].</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=29263">
</A>
</P>
<DIV>
<IMG SRC="CH07-3.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=29265">
</A>
FIGURE 7.3 <A NAME="27071">
</A>
Measuring the delay of a net. (a) An RC tree. (b) The waveforms as a result of closing the switch at<SPAN CLASS="EquationVariables">
t </SPAN>
= 0.</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=10324">
</A>
The current in branch <SPAN CLASS="EquationVariables">
k </SPAN>
of the network is </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnRight">
<A NAME="pgfId=46762">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=46764">
</A>
</P>
</TD>
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