ch07.5.htm

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<TITLE> 7.5&nbsp;Altera MAX 9000</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->



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<P>[&nbsp;<A HREF="CH07.htm">Chapter&nbsp;start</A>&nbsp;]&nbsp;[&nbsp;<A HREF="CH07.4.htm">Previous&nbsp;page</A>&nbsp;]&nbsp;[&nbsp;<A HREF="CH07.6.htm">Next&nbsp;page</A>&nbsp;]</P><!--#include file="AmazonAsic.html"--><HR></DIV>

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7.5&nbsp;<A NAME="37674">

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Altera MAX 9000</H1>

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Figure&nbsp;7.9</A>

 shows the Altera MAX 9000 interconnect architecture. The size of the MAX 9000 LAB arrays varies between 4 <SPAN CLASS="Symbol">

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 5 (rows <SPAN CLASS="Symbol">

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 columns) for the EPM9320 and 7 <SPAN CLASS="Symbol">

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 5 for the EPM9560. The MAX 9000 is an extremely coarse-grained architecture, typical of complex PLDs, but the LABs themselves have a finer structure. Sometimes we say that complex PLDs with arrays (LABs in the Altera MAX family) that are themselves arrays (of macrocells) have a <SPAN CLASS="Definition">

dual-grain architecture</SPAN>

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FIGURE&nbsp;7.9&nbsp;<A NAME="36048">

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The Altera MAX 9000 interconnect scheme. (a)&nbsp; A 4 <SPAN CLASS="Symbol">

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 5 array of Logic Array Blocks (LABs), the same size as the EMP9400 chip. (b)&nbsp;A simplified block diagram of the interconnect architecture showing the connection of the FastTrack buses to a LAB.</P>

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In <A HREF="CH07.5.htm#36048" CLASS="XRef">

Figure&nbsp;7.9</A>

(b), boxes A, B, and C represent the interconnection between the FastTrack buses and the 16 macrocells in each LAB:</P>

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Box A connects a macrocell to one row channel.</LI>

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Box B connects three column channels to two row channels.</LI>

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Box C connects a macrocell to three column channels.</LI>

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