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<TITLE> 7.2 Xilinx LCA</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
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<H1 CLASS="Heading1">
<A NAME="pgfId=1571">
</A>
7.2 <A NAME="26326">
</A>
Xilinx LCA</H1>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=13178">
</A>
<A HREF="CH07.2.htm#42123" CLASS="XRef">
Figure 7.5</A>
shows the hierarchical Xilinx LCA interconnect architecture. </P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=16640">
</A>
The <A NAME="marker=10915">
</A>
vertical lines and <A NAME="marker=10916">
</A>
horizontal lines run between CLBs. </LI>
<LI CLASS="BulletList">
<A NAME="pgfId=16639">
</A>
The <A NAME="marker=10917">
</A>
general-purpose interconnect joins <A NAME="marker=10918">
</A>
switch boxes (also known as <A NAME="marker=10919">
</A>
magic boxes or <A NAME="marker=10920">
</A>
switching matrices). </LI>
<LI CLASS="BulletList">
<A NAME="pgfId=1613">
</A>
The <A NAME="marker=1611">
</A>
long lines run across the entire chip. It is possible to form internal buses using long lines and the three-state buffers that are next to each CLB.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=1621">
</A>
The <A NAME="marker=1619">
</A>
direct connections (not used on the XC4000) bypass the switch matrices and directly connect adjacent CLBs.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=1631">
</A>
The <A NAME="marker=1627">
</A>
Programmable Interconnection Points (<A NAME="marker=1630">
</A>
PIP<A NAME="marker=29166">
</A>
s) are programmable pass transistors that connect the CLB inputs and outputs to the routing network. </LI>
<LI CLASS="BulletLast">
<A NAME="pgfId=14071">
</A>
The <A NAME="marker=14075">
</A>
bidirectional (<A NAME="marker=14076">
</A>
BIDI<A NAME="marker=14077">
</A>
) interconnect buffers restore the logic level and logic strength on long interconnect paths. </LI>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=26781">
</A>
</P>
<DIV>
<IMG SRC="CH07-5.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=26784">
</A>
FIGURE 7.5 <A NAME="42123">
</A>
Xilinx LCA interconnect. (a) The LCA architecture (notice the matrix element size is larger than a CLB). (b) A simplified representation of the interconnect resources. Each of the lines is a bus.</P>
</TD>
</TR>
</TABLE>
</UL>
<P CLASS="Body">
<A NAME="pgfId=27824">
</A>
<A HREF="CH07.2.htm#38131" CLASS="XRef">
Table 7.3</A>
shows the interconnect data for an XC3020, a typical Xilinx LCA FPGA, that uses two-level metal interconnect. <A HREF="CH07.2.htm#30356" CLASS="XRef">
Figure 7.6</A>
shows the switching matrix. Programming a switch matrix allows a number of different connections between the general-purpose interconnect. </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="TableTitle">
<A NAME="pgfId=27829">
</A>
TABLE 7.3 <A NAME="38131">
</A>
XC3000 interconnect parameters.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=27833">
</A>
<SPAN CLASS="TableHeads">
Parameter</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=27835">
</A>
<SPAN CLASS="TableHeads">
XC3020</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=27837">
</A>
Technology</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=27839">
</A>
1.0 <SPAN CLASS="Symbol">
m</SPAN>
m, <SPAN CLASS="Symbol">
l</SPAN>
= 0.5 <SPAN CLASS="Symbol">
m</SPAN>
m</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=27841">
</A>
Die height</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=27843">
</A>
220 mil </P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=27845">
</A>
Die width</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=27847">
</A>
180 mil </P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=27849">
</A>
Die area</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=27851">
</A>
39,600 mil<SUP CLASS="Superscript">
2</SUP>
= 102 M<SPAN CLASS="Symbol">
l</SPAN>
<SUP CLASS="Superscript">
2</SUP>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=27853">
</A>
CLB matrix height (Y)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=27855">
</A>
480 <SPAN CLASS="Symbol">
m</SPAN>
m = 960 <SPAN CLASS="Symbol">
l</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=27857">
</A>
CLB matrix width (X)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=27859">
</A>
370 <SPAN CLASS="Symbol">
m</SPAN>
m = 740 <SPAN CLASS="Symbol">
l</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=27861">
</A>
CLB matrix area (X <SPAN CLASS="Symbol">
¥ </SPAN>
Y)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=27863">
</A>
17,600 <SPAN CLASS="Symbol">
m</SPAN>
m<SUP CLASS="Superscript">
2</SUP>
= 710 k<SPAN CLASS="Symbol">
l</SPAN>
<SUP CLASS="Superscript">
2</SUP>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=27865">
</A>
Matrix transistor resistance, R<SUB CLASS="Subscript">
P1</SUB>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=27867">
</A>
0.5–1k <SPAN CLASS="Symbol">
W</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=27869">
</A>
Matrix transistor parasitic capacitance, C<SUB CLASS="Subscript">
P1</SUB>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=27871">
</A>
0.01–0.02 pF</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=27873">
</A>
PIP transistor resistance, R<SUB CLASS="Subscript">
P2</SUB>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=27875">
</A>
0.5–1k <SPAN CLASS="Symbol">
W</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=27877">
</A>
PIP transistor parasitic capacitance, C<SUB CLASS="Subscript">
P2</SUB>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=27879">
</A>
0.01–0.02 pF</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=27881">
</A>
Single-length line (X, Y)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=27883">
</A>
370 <SPAN CLASS="Symbol">
m</SPAN>
m, 480 <SPAN CLASS="Symbol">
m</SPAN>
m</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=27885">
</A>
Single-length line capacitance: C <SUB CLASS="Subscript">
LX</SUB>
, C<SUB CLASS="Subscript">
LY</SUB>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=27887">
</A>
0.075 pF, 0.1 pF</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=27889">
</A>
Horizontal Longline (8X)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=27891">
</A>
8 cols. = 2960 <SPAN CLASS="Symbol">
m</SPAN>
m</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=27893">
</A>
Horizontal Longline metal capacitance, C<SUB CLASS="Subscript">
LL</SUB>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=27895">
</A>
0.6 pF</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=27921">
</A>
In <A HREF="CH07.2.htm#30356" CLASS="XRef">
Figure 7.6</A>
(d), (g), and (h): </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=27912">
</A>
</P>
<DIV>
<IMG SRC="CH07-6.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=27916">
</A>
FIGURE 7.6 <A NAME="30356">
</A>
Components of interconnect delay in a Xilinx LCA array. (a) A portion of the interconnect around the CLBs. (b) A switching matrix. (c) A detailed view inside the switching matrix showing the pass-transistor arrangement. (d) The equivalent circuit for the connection between nets 6 and 20 using the matrix. (e) A view of the interconnect at a Programmable Interconnection Point (PIP). (f) and (g) The equivalent schematic of a PIP connection. (h) The complete RC delay path.</P>
</TD>
</TR>
</TABLE>
<UL>
<LI CLASS="BulletList">
<A NAME="pgfId=12762">
</A>
<SPAN CLASS="EquationNumber">
C1</SPAN>
= <SPAN CLASS="EquationNumber">
3CP1</SPAN>
+ <SPAN CLASS="EquationNumber">
3CP2</SPAN>
+ 0.<SPAN CLASS="EquationNumber">
5C</SPAN>
<SUB CLASS="Subscript">
LX</SUB>
is the parasitic capacitance due to the switch matrix and PIPs (F4, C4, G4) for CLB1, and half of the line capacitance for the double-length line adjacent to CLB1.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=13210">
</A>
<SPAN CLASS="EquationNumber">
C</SPAN>
<SUB CLASS="Subscript">
P1</SUB>
and <SPAN CLASS="EquationNumber">
R</SPAN>
<SUB CLASS="Subscript">
P1</SUB>
are the switching-matrix parasitic capacitance and resistance.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=13213">
</A>
<SPAN CLASS="EquationNumber">
C</SPAN>
<SUB CLASS="Subscript">
P2</SUB>
and <SPAN CLASS="EquationNumber">
R</SPAN>
<SUB CLASS="Subscript">
P2</SUB>
are the parasitic capacitance and resistance for the PIP connecting YQ of CLB1 and F4 of CLB3.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=13215">
</A>
<SPAN CLASS="EquationNumber">
C2</SPAN>
= 0.<SPAN CLASS="EquationNumber">
5CLX</SPAN>
+ <SPAN CLASS="EquationNumber">
CLX</SPAN>
accounts for half of the line adjacent to CLB1 and the line adjacent to CLB2.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=13216">
</A>
<SPAN CLASS="EquationNumber">
C</SPAN>
<SUB CLASS="Subscript">
3</SUB>
= 0.<SPAN CLASS="EquationNumber">
5C</SPAN>
<SUB CLASS="Subscript">
LX </SUB>
accounts for half of the line adjacent to CLB3.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=13217">
</A>
<SPAN CLASS="EquationNumber">
C</SPAN>
<SUB CLASS="Subscript">
4</SUB>
= 0.<SPAN CLASS="EquationNumber">
5C</SPAN>
<SUB CLASS="Subscript">
LX</SUB>
+<SPAN CLASS="EquationNumber">
3C</SPAN>
<SUB CLASS="Subscript">
P2</SUB>
+ <SPAN CLASS="EquationNumber">
C</SPAN>
<SUB CLASS="Subscript">
LX</SUB>
+<SPAN CLASS="EquationNumber">
3C</SPAN>
<SUB CLASS="Subscript">
P1</SUB>
accounts for half of the line adjacent to CLB3, the PIPs of CLB3 (C4, G4, YQ), and the rest of the line and switch matrix capacitance following CLB3.</LI>
</UL>
<P CLASS="Body">
<A NAME="pgfId=12779">
</A>
We can determine Elmore’s time constant for the connection shown in <A HREF="CH07.2.htm#30356" CLASS="XRef">
Figure 7.6</A>
as </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnRight">
<A NAME="pgfId=47436">
</A>
<SPAN CLASS="Symbol">
t</SPAN>
<SUB CLASS="SubscriptVariable">
D</SUB>
<SUB CLASS="Subscript">
</SUB>
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