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<H1 CLASS="ChapterTitle">
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PROGRAMMABLE <BR>
ASIC <BR>
INTERCONNECT</H1>
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All FPGAs contain some type of <A NAME="marker=1294">
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<SPAN CLASS="Definition">
programmable interconnect</SPAN>
. The structure and complexity of the interconnect is largely determined by the programming technology and the architecture of the basic logic cell. The raw material that we have to work with in building the interconnect is aluminum-based metallization, which has a sheet resistance of approximately 50 m<SPAN CLASS="Symbol">
W</SPAN>
/square and a line capacitance of 0.2 pFcm<SUP CLASS="Superscript">
–1</SUP>
. The first programmable ASICs were constructed using two layers of metal; newer programmable ASICs use three or more layers of metal interconnect.</P>
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7.1 Actel ACT</A>
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7.2 Xilinx LCA</A>
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7.3 Xilinx EPLD</A>
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7.4 Altera MAX 5000 and 7000</A>
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7.5 Altera MAX 9000</A>
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7.6 Altera FLEX</A>
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7.7 Summary</A>
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7.8 Problems</A>
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7.9 Bibliography</A>
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7.10 References</A>
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