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<TITLE> 7.4&nbsp;Altera MAX 5000 and 7000</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->



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<P>[&nbsp;<A HREF="CH07.htm">Chapter&nbsp;start</A>&nbsp;]&nbsp;[&nbsp;<A HREF="CH07.3.htm">Previous&nbsp;page</A>&nbsp;]&nbsp;[&nbsp;<A HREF="CH07.5.htm">Next&nbsp;page</A>&nbsp;]</P><!--#include file="AmazonAsic.html"--><HR></DIV>

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7.4&nbsp;<A NAME="22278">

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Altera MAX 5000 and 7000</H1>

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Altera MAX 5000 devices (except the EPM5032, which has only one LAB) and all MAX 7000 devices use a <A NAME="marker=29306">

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Programmable Interconnect Array </SPAN>

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PIA</SPAN>

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), shown in <A HREF="CH07.4.htm#24579" CLASS="XRef">

Figure&nbsp;7.8</A>

. The PIA is a cross-point switch for logic signals traveling between LABs. The advantages of this architecture (which uses a fixed number of connections) over programmable interconnection schemes (which use a variable number of connections) is the fixed routing delay. An additional benefit of the simpler nature of a large regular interconnect structure is the simplification and improved speed of the placement and routing software.</P>

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FIGURE&nbsp;7.8&nbsp;<A NAME="24579">

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 A simplified block diagram of the Altera MAX interconnect scheme. (a)&nbsp;The PIA (Programmable Interconnect Array) is deterministic&#8212;delay is independent of the path length. (b)&nbsp;Each LAB (Logic Array Block) contains a programmable AND array. (c)&nbsp;Interconnect timing within a LAB is also fixed.</P>

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Figure&nbsp;7.8</A>

(a) illustrates that the delay between any two LABs, t<SUB CLASS="Subscript">

PIA</SUB>

, is fixed. The delay between LAB1 and LAB2 (which are adjacent) is the same as the delay between LAB1 and LAB6 (on opposite corners of the die). It may seem rather strange to slow down all connections to the speed of the longest possible connection&#8212;a large penalty to pay to achieve a deterministic architecture. However, it gives Altera the opportunity to highly optimize all of the connections since they are completely fixed.</P>

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