ch07.7.htm

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 </A>
<SPAN CLASS="TableHeads">
Interconnect inside logic cells</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30907">
 </A>
EPROM</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30909">
 </A>
EPROM</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30911">
 </A>
Metal&#8211;metal antifuse</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30913">
 </A>
Poly&#8211;diffusion antifuse</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30915">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30917">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30919">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30921">
 </A>
&nbsp;</P>
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30922">
 </A>
&nbsp;</P>
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30923">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30925">
 </A>
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30927">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=30929">
 </A>
<SPAN CLASS="TableHeads">
Crosspoint (CP20K)</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=30931">
 </A>
<SPAN CLASS="TableHeads">
Altera MAX </SPAN>
</P>
<P CLASS="Table">
<A NAME="pgfId=30932">
 </A>
<SPAN CLASS="TableHeads">
(MAX 7000)</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=30934">
 </A>
<SPAN CLASS="TableHeads">
Atmel (AT6000)</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=30936">
 </A>
<SPAN CLASS="TableHeads">
Xilinx LCA (XC5200)</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30938">
 </A>
<SPAN CLASS="TableHeads">
Interconnect between logic cells </SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30940">
 </A>
Programmable highly</P>
<P CLASS="TableLeft">
<A NAME="pgfId=30941">
 </A>
interconnected matrix</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30943">
 </A>
Fixed cross-bar PIA (Programmable Interconnect Architecture)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30945">
 </A>
Programmable regular, local, and express bus scheme with line repeaters</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30947">
 </A>
Switch box, PIPs (Programmable Interconnect Points), 3-state internal bus, and long lines</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30949">
 </A>
<SPAN CLASS="TableHeads">
Interconnect delay</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30951">
 </A>
Variable</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30953">
 </A>
Fixed</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30955">
 </A>
Variable</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30957">
 </A>
Variable</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30959">
 </A>
<SPAN CLASS="TableHeads">
Interconnect inside logic cells</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30961">
 </A>
Metal&#8211;metal </P>
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30962">
 </A>
antifuse</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30964">
 </A>
EEPROM</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30966">
 </A>
SRAM</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30968">
 </A>
16-bit SRAM </P>
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30969">
 </A>
LUT</P>
</TD>
</TR>
</TABLE>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="4">
<P CLASS="TableTitle">
<A NAME="pgfId=30977">
 </A>
TABLE&nbsp;7.6&nbsp;<A NAME="24465">
 </A>
Programmable ASIC interconnect (continued).</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30985">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=30987">
 </A>
<SPAN CLASS="TableHeads">
Xilinx (XC8100)</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=30989">
 </A>
<SPAN CLASS="TableHeads">
Lucent ORCA 2C</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=30991">
 </A>
<SPAN CLASS="TableHeads">
Altera FLEX 8000/10k</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30993">
 </A>
<SPAN CLASS="TableHeads">
Interconnect between logic cells </SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30995">
 </A>
Channeled array with </P>
<P CLASS="TableLeft">
<A NAME="pgfId=30996">
 </A>
segmented routing, long lines. Programmable fully populated antifuse matrix.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30998">
 </A>
Switch box, SRAM programmable interconnect, 3-state internal bus, and long lines</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=31000">
 </A>
Row and column FastTrack between LABs</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=31002">
 </A>
<SPAN CLASS="TableHeads">
Interconnect delay</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=31004">
 </A>
Variable</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=31006">
 </A>
Variable</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=31008">
 </A>
Fixed with small variation in delay in row FastTrack </P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=31010">
 </A>
<SPAN CLASS="TableHeads">
Interconnect inside logic cells</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=31012">
 </A>
Antifuse</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=31014">
 </A>
SRAM LUTs and MUXs</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=31016">
 </A>
LAB local interconnect between LEs. 16-bit SRAM LUT in LE.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=31018">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=31020">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=31022">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=31024">
 </A>
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=31026">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=31028">
 </A>
<SPAN CLASS="TableHeads">
AMD MACH&nbsp;5</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=31030">
 </A>
<SPAN CLASS="TableHeads">
Actel 3200DX</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=31032">
 </A>
<SPAN CLASS="TableHeads">
Altera MAX 9000</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=31034">
 </A>
<SPAN CLASS="TableHeads">
Interconnect between logic cells </SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=31036">
 </A>
EPROM programmable array</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=31038">
 </A>
Channeled gate array</P>
<P CLASS="TableLeft">
<A NAME="pgfId=31039">
 </A>
with segmented routing, long lines</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=31041">
 </A>
Row and column FastTrack between LABs</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=31043">
 </A>
<SPAN CLASS="TableHeads">
Interconnect delay</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=31045">
 </A>
Fixed</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=31047">
 </A>
Variable</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=31049">
 </A>
Fixed</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=31051">
 </A>
<SPAN CLASS="TableHeads">
Interconnect inside logic cells</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=31053">
 </A>
EPROM</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=31055">
 </A>
Poly&#8211;diffusion antifuse</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=31057">
 </A>
Programmable AND array inside LAB, EEPROM MUXes</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=29453">
 </A>
The key points covered in this chapter are:</P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=13971">
 </A>
The difference between deterministic and nondeterministic interconnect</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=14091">
 </A>
Estimating interconnect delay</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=13972">
 </A>
Elmore&#8217;s constant</LI>
</UL>
<P CLASS="Body">
<A NAME="pgfId=13981">
 </A>
Next, in Chapter&nbsp;8, we shall cover the software you need to design with the various FPGA families and explain how FPGAs are programmed.</P>
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