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<H1 CLASS="Heading1">
<A NAME="pgfId=1826">
</A>
7.7 <A NAME="24940">
</A>
Summary</H1>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=16022">
</A>
The RC product of the parasitic elements of an antifuse and a pass transistor are not too different. However, an SRAM cell is much larger than an antifuse which leads to coarser interconnect architectures for SRAM-based programmable ASICs. The EPROM device lends itself to large wired-logic structures. These differences in programming technology lead to different architectures:</P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=16023">
</A>
The antifuse FPGA architectures are dense and regular.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=16024">
</A>
The SRAM architectures contain nested structures of interconnect resources.</LI>
<LI CLASS="BulletLast">
<A NAME="pgfId=30788">
</A>
The complex PLD architectures use long interconnect lines but achieve deterministic routing.</LI>
</UL>
<P CLASS="Body">
<A NAME="pgfId=30799">
</A>
<A HREF="CH07.7.htm#37283" CLASS="XRef">
Table 7.4</A>
is a look-up table for Tables <A HREF="CH07.7.htm#33085" CLASS="XRef">
7.5</A>
and <A HREF="CH07.7.htm#24465" CLASS="XRef">
7.6</A>
, which summarize the features of the logic cells used by the various FPGA vendors. </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="5">
<P CLASS="TableTitle">
<A NAME="pgfId=31391">
</A>
TABLE 7.4 <A NAME="37283">
</A>
I/O Cell Tables.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=31401">
</A>
<SPAN CLASS="TableHeads">
Table</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=31403">
</A>
<SPAN CLASS="TableHeads">
Programmable ASIC family</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=31405">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=31407">
</A>
<SPAN CLASS="TableHeads">
Table</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=31409">
</A>
<SPAN CLASS="TableHeads">
Programmable ASIC family</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=31414">
</A>
<A HREF="CH07.7.htm#33085" CLASS="XRef">
Table 7.5</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=31416">
</A>
Actel (ACT 1)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=31417">
</A>
Xilinx (XC3000)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=31418">
</A>
Actel (ACT 2)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=31419">
</A>
Xilinx (XC4000)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=31420">
</A>
Altera MAX (EPM 5000)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=31421">
</A>
Xilinx EPLD (XC7200/7300)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=31482">
</A>
Actel (ACT 3)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=31422">
</A>
QuickLogic (pASIC 1)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=31423">
</A>
Crosspoint (CP20K)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=31424">
</A>
Altera MAX (EPM 7000)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=31425">
</A>
Atmel (AT6000)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=31491">
</A>
Xilinx LCA (XC5200)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=31427">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=31432">
</A>
<A HREF="CH07.7.htm#24465" CLASS="XRef">
Table 7.6</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=31500">
</A>
Xilinx (XC8100)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=31498">
</A>
Lucent ORCA (2C)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=31504">
</A>
Altera FLEX (8000/10k)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=31437">
</A>
AMD MACH 5</P>
<P CLASS="TableLeft">
<A NAME="pgfId=31438">
</A>
Actel 3200DX</P>
<P CLASS="TableLeft">
<A NAME="pgfId=31439">
</A>
Altera MAX (EPM 9000)</P>
</TD>
</TR>
</TABLE>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="5">
<P CLASS="TableTitle">
<A NAME="pgfId=30805">
</A>
TABLE 7.5 <A NAME="33085">
</A>
Programmable ASIC interconnect.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=30815">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=30817">
</A>
<SPAN CLASS="TableHeads">
Actel (ACT 1)</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=30819">
</A>
<SPAN CLASS="TableHeads">
Xilinx (XC3000)</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=30821">
</A>
<SPAN CLASS="TableHeads">
Actel (ACT 2)</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=30823">
</A>
<SPAN CLASS="TableHeads">
Xilinx (XC4000)</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30825">
</A>
<SPAN CLASS="TableHeads">
Interconnect between logic cells (tracks</SPAN>
<SPAN CLASS="TableHeads">
=</SPAN>
<SPAN CLASS="TableHeads">
trks)</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30827">
</A>
Channeled array with segmented routing, long lines:</P>
<P CLASS="TableLeft">
<A NAME="pgfId=30828">
</A>
25 trks/ch. (horiz.); 13 trks/ch. (vert.); </P>
<P CLASS="TableLeft">
<A NAME="pgfId=30829">
</A>
< 4 antifuses/path</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30831">
</A>
Switch box, PIPs (Programmable Interconnect Points), 3-state internal bus, and long lines</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30833">
</A>
Channeled array with segmented routing, long lines: </P>
<P CLASS="TableLeft">
<A NAME="pgfId=30834">
</A>
36 trks/ch. (horiz.); 15 trks/ch. (vert.);</P>
<P CLASS="TableLeft">
<A NAME="pgfId=30835">
</A>
< 4 antifuses/path</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30837">
</A>
Switch box, PIPs (Programmable Interconnect Points), 3-state internal bus, and long lines</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30839">
</A>
<SPAN CLASS="TableHeads">
Interconnect delay</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30841">
</A>
Variable</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30843">
</A>
Variable</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30845">
</A>
Variable</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30847">
</A>
Variable</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30849">
</A>
<SPAN CLASS="TableHeads">
Interconnect inside logic cells</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30851">
</A>
Poly–diffusion antifuse</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30853">
</A>
32-bit SRAM LUT</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30855">
</A>
Poly–diffusion antifuse</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30857">
</A>
32-bit SRAM</P>
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30858">
</A>
LUT</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30860">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30862">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30864">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30866">
</A>
</P>
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30867">
</A>
</P>
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30868">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30870">
</A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=30872">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=30874">
</A>
<SPAN CLASS="TableHeads">
Altera (MAX 5000)</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=30876">
</A>
<SPAN CLASS="TableHeads">
Xilinx EPLD </SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=30878">
</A>
<SPAN CLASS="TableHeads">
QuickLogic (pASIC 1)</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=30880">
</A>
<SPAN CLASS="TableHeads">
Actel (ACT 3)</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30882">
</A>
<SPAN CLASS="TableHeads">
Interconnect between logic cells </SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30884">
</A>
Cross-bar PIA </P>
<P CLASS="TableLeft">
<A NAME="pgfId=30885">
</A>
(Programmable Interconnect Architecture) using EPROM programmable-AND array</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30887">
</A>
UIM (Universal Interconnect Matrix) using EPROM programmable-AND array</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30889">
</A>
Programmable</P>
<P CLASS="TableLeft">
<A NAME="pgfId=30890">
</A>
fully populated </P>
<P CLASS="TableLeft">
<A NAME="pgfId=30891">
</A>
antifuse matrix </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30893">
</A>
Channeled array with segmented routing, long lines: <4 antifuses/path</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30895">
</A>
<SPAN CLASS="TableHeads">
Interconnect delay</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30897">
</A>
Fixed</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30899">
</A>
Fixed</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30901">
</A>
Variable</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30903">
</A>
Variable</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=30905">
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