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<TITLE> 7.3 Xilinx EPLD</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
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<H1 CLASS="Heading1">
<A NAME="pgfId=31543">
</A>
7.3 <A NAME="37489">
</A>
Xilinx EPLD</H1>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=31545">
</A>
The Xilinx EPLD family uses an interconnect bus known as <A NAME="marker=31544">
</A>
<SPAN CLASS="Definition">
Universal Interconnection Module</SPAN>
(<A NAME="marker=31546">
</A>
<SPAN CLASS="Definition">
UIM</SPAN>
) to distribute signals within the FPGA. The UIM, shown in <A HREF="CH07.2.htm#26676" CLASS="XRef">
Figure 7.7</A>
, is a programmable AND array with constant delay from any input to any output. In <A HREF="CH07.2.htm#26676" CLASS="XRef">
Figure 7.7</A>
:</P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=16100">
</A>
<SPAN CLASS="EquationNumber">
C</SPAN>
<SUB CLASS="Subscript">
G</SUB>
is the fixed gate capacitance of the EPROM device.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=16101">
</A>
<SPAN CLASS="EquationNumber">
C</SPAN>
<SUB CLASS="Subscript">
D</SUB>
is the fixed drain parasitic capacitance of the EPROM device.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=16102">
</A>
<SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
B</SUB>
is the variable horizontal bus (“bit” line) capacitance.</LI>
<LI CLASS="BulletLast">
<A NAME="pgfId=16103">
</A>
<SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
W</SUB>
is the variable vertical bus (“word” line) capacitance.</LI>
</UL>
<P CLASS="Body">
<A NAME="pgfId=16130">
</A>
<A HREF="CH07.2.htm#26676" CLASS="XRef">
Figure 7.7</A>
shows the UIM has 21 output connections to each FB.<A HREF="#pgfId=16415" CLASS="footnote">
1</A>
Thus the XC7272 UIM (with a 4 <SPAN CLASS="Symbol">
¥</SPAN>
2 array of eight FBs as shown in <A HREF="CH07.2.htm#26676" CLASS="XRef">
Figure 7.7</A>
) has 168 (8 <SPAN CLASS="Symbol">
¥</SPAN>
21) output connections. Most (but not all) of the nine I/O cells attached to each FB have two input connections to the UIM, one from a chip input and one feedback from the macrocell output. For example, the XC7272 has 18 I/O cells that are outputs only and thus have only one connection to the UIM, so <SPAN CLASS="EquationVariables">
n</SPAN>
= (18 <SPAN CLASS="Symbol">
¥</SPAN>
8) – 18 = 126 input connections. Now we can calculate the number of tracks in the UIM: the XC7272, for example, has <SPAN CLASS="EquationVariables">
H</SPAN>
= 126 tracks and <SPAN CLASS="EquationVariables">
V</SPAN>
= 168/2 = 84 tracks. The actual physical height, <SPAN CLASS="EquationVariables">
V</SPAN>
, of the UIM is determined by the size of the FBs, and is close to the die height. </P>
<P CLASS="Body">
<A NAME="pgfId=27670">
</A>
The UIM ranges in size with the number of FBs. For the smallest XC7236 (with a 2 <SPAN CLASS="Symbol">
¥</SPAN>
2 array of four FBs), the UIM has <SPAN CLASS="EquationVariables">
n</SPAN>
= 68 inputs and 84 outputs. For the XC73108 (with a 6 <SPAN CLASS="Symbol">
¥</SPAN>
2 array of 12 FBs), the UIM has <SPAN CLASS="EquationVariables">
n</SPAN>
= 198 inputs. The UIM is a large array with large parasitic capacitance; it employs a highly optimized structure that uses EPROM devices and a <A NAME="marker=27671">
</A>
sense amplifier at each output. The signal swing on the UIM uses less than the full <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
= 5 V to reduce the interconnect delay.</P>
<HR>
<DIV CLASS="footnotes">
<DIV CLASS="footnote">
<P CLASS="Footnote">
<SPAN CLASS="footnoteNumber">
1.</SPAN>
<A NAME="pgfId=16415">
</A>
1994 data book p. 3-62 and p. 3-78.</P>
</DIV>
</DIV>
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