ch17.8.htm
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<A NAME="pgfId=1526">
</A>
Murarka, S. P. 1993. <SPAN CLASS="BookTitle">
Metallization: Theory and Practice for VLSI and ULSI.</SPAN>
Stoneham, MA: Butterworth-Heinemann, 250 p. ISBN 0-7506-9001-1. TK7874.M868. Includes chapters on metal properties; crystal structure; electrical and mechanical properties; diffusion and reaction in thin metallic films; deposition method and techniques; pattern definition; packaging applications; reliability. [<A HREF="CH17.7.htm#Murarka93" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=71516">
</A>
Najm, F. N. 1994. “A survey of power estimation techniques in VLSI circuits.” <SPAN CLASS="BookTitle">
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,</SPAN>
Vol. 2, no. 4, pp. 446–55. 43 references. [<A HREF="CH17.7.htm#[Najm, 1994]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=23549">
</A>
O’Brien, P. R., and T. L. Savarino. 1989. “Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation.” In <SPAN CLASS="BookTitle">
Proceedings of the International Conference on Computer-Aided Design,</SPAN>
pp. 512–515. Describes SPF PI segment model. [p<A HREF="CH17.4.htm#O誃rien89a" CLASS="XRef">
reference location</A>
, <A HREF="CH17.6.htm#O誃rien89b" CLASS="XRef">
974</A>
]. </P>
<P CLASS="Reference">
<A NAME="pgfId=72370">
</A>
Ohtsuki, T. (Ed.). 1986. <SPAN CLASS="BookTitle">
Layout Design and Verification.</SPAN>
New York: Elsevier Science, ISBN 0444878947. TK7874.L318. Includes nine papers on CAD tools and algorithms: “Layout strategy, standardisation, and CAD tools,” Ueda, Kasai, and Sudo; “Layout compaction,” Mylynski and Sung; “Layout verification,” Yoshida; “Partitioning, assignment and placement,” Goto and Matsuda; “Computational complexity of layout problems,” Shing and Hu; “Computational and geometry algorithms,” Asano, Sato, and Ohtsuki; an excellent survey and tutorial paper by M. Burstein — “Channel routing;” “Maze-running and line-search algorithms,” a good, easily readable paper on detailed routing by Ohtsuki; and a more mathematical paper, “Global routing,” by Kuh and Marek-Sadowska. [pp. 932, 957]</P>
<P CLASS="Reference">
<A NAME="pgfId=42217">
</A>
Pillage, L., et al. 1994. <SPAN CLASS="BookTitle">
Electronic Circuit and System Simulation Methods.</SPAN>
New York: McGraw-Hill, 392 p. ISBN 0-07-050169-6. TK7874.P52. [<A HREF="CH17.7.htm#[Pillage, 1994]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=72322">
</A>
Preas, B. T., and M. J. Lorenzetti. 1988. <SPAN CLASS="BookTitle">
Physical Design Automation of VLSI Systems.</SPAN>
Menlo Park, CA: Benjamin-Cummings, 510 p. ISBN 0805304129. TK7874.P47. Chapters on: physical design automation; interconnection analysis, logic partitioning; placement, assignment and floorplanning; routing; symbolic layout and compaction; module generation and silicon compilation; layout analysis and verification; knowledge-based physical design automation; combinatatorial complexity of layout problems. [<A HREF="CH17.7.htm#[Preas and Lorenzetti, 1988]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=72703">
</A>
Ravikumar, C. P. 1996. <SPAN CLASS="BookTitle">
Parallel Methods for VLSI Layout Design.</SPAN>
Norwood, NJ: Ablex, 195 p. ISBN 0893918288. TK7874.R39. [<A HREF="CH17.7.htm#[Ravikumar, 1996]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=1558">
</A>
Roy, K. 1993. “A bounded search algorithm for segmented channel routing for FPGA’s and associated channel architecture issues.” <SPAN CLASS="BookTitle">
IEEE Transactions on Computer-Aided Design,</SPAN>
Vol. 12, no. 11, pp. 1695–1704. [<A HREF="CH17.7.htm#Roy93" CLASS="XRef">
reference location</A>
].</P>
<P CLASS="Reference">
<A NAME="pgfId=72488">
</A>
Sait, S. M., and H. Youssef. 1995. <SPAN CLASS="BookTitle">
VLSI Physical Design Automation, Theory and Practice.</SPAN>
New York: IEEE Press/McGraw-Hill copublication, 426 p. ISBN 0-07-707742-3. TK7874.75.S24. Covers floorplanning, placement, and routing. [<A HREF="CH17.7.htm#[Sait and Youssef, 1995]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=15271">
</A>
Sakurai, T., and K. Tamaru. 1983. “Simple formulas for two- and three-dimensional capacitances.” <SPAN CLASS="BookTitle">
IEEE Transactions on Electron Devices</SPAN>
. Vol. 30, no. 2. [<A HREF="CH17.6.htm#Sakurai83" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=72609">
</A>
Sapatnekar, S. S., and S.-M. Kang. 1993. <SPAN CLASS="BookTitle">
Design Automation for Timing-Driven Layout Synthesis.</SPAN>
Boston: Kluwer, 269 p. ISBN 0792392817. TK7871.99.M44.S37. 19 pages of references. [<A HREF="CH17.7.htm#[Sapatnekar and Kang, 1993]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=72403">
</A>
Sarrafzadeh, M., and C. K. Wong. 1996. <SPAN CLASS="BookTitle">
An Introduction to VLSI Physical Design. </SPAN>
New York: McGraw-Hill, 334 p. ISBN 0070571945. TK7874.75.S27. 17 pages of references. [<A HREF="CH17.7.htm#[Sarrafzadeh and Wong, 1996]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=72724">
</A>
Shenai, K. (Ed.). 1991. <SPAN CLASS="BookTitle">
VLSI Metallization: Physics and Technologies.</SPAN>
Boston: Artech House, 529 p. ISBN 0890065012. TK7872.C68.V58. [<A HREF="CH17.7.htm#[Shenai, 1991]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=72600">
</A>
Sherwani, N. A. 1993. <SPAN CLASS="BookTitle">
Algorithms for VLSI Physical Design Automation.</SPAN>
2nd ed. Norwell, MA: Kluwer, 538 p. ISBN 0-7923-9294-9. TK874.S455. See also the first edition. [<A HREF="CH17.7.htm#[Sherwani, 1993]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=39535">
</A>
Sherwani, N. A., et al. 1995. <SPAN CLASS="BookTitle">
Routing in the Third Dimension: From VLSI Chips to MCMs.</SPAN>
New York: IEEE Press. ISBN 0-7803-1089-6. TK7874.75.R68. Reviews two-layer and multilayer routing algorithms. Contains chapters on: graphs and basic algorithms; channel routing; routing models; routing algorithms for two- and three-layer processes and MCMs. [<A HREF="CH17.7.htm#[Sherwani, 1995]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=72581">
</A>
Taylor, G., and G. Russell. (Eds.). 1992. <SPAN CLASS="BookTitle">
Algorithmic and Knowledge Based CAD for VLSI.</SPAN>
London: P. Peregrinus, 273 p. ISBN 086341267X. TK7874.A416. [<A HREF="CH17.7.htm#[Taylor and Russell, 1992]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=42244">
</A>
Veendrick, H. J. M. 1984. “Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits.” <SPAN CLASS="BookTitle">
IEEE Journal of Solid-State Circuits,</SPAN>
Vol. 19, no. 4, pp. 468–473. [<A HREF="CH17.3.htm#Veendrick84" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=72269">
</A>
Young, D., and A. Christou. 1994. “Failure mechanism models for electromigration.” <SPAN CLASS="BookTitle">
IEEE Transactions on Reliability,</SPAN>
Vol. 43, no. 2, pp. 186–192. A tutorial on electromigration and its relation to microstructure. [p<A HREF="CH17.3.htm#[Young and Christou, 1994]" CLASS="XRef">
reference location</A>
, 957]</P>
<P CLASS="Reference">
<A NAME="pgfId=72642">
</A>
Zobrist, G. W. (Ed.). 1994. <SPAN CLASS="BookTitle">
Routing, Placement, and Partitioning.</SPAN>
Norwood, NJ: Ablex, 293 p. ISBN 0893917842. TK7874.R677. [<A HREF="CH17.7.htm#[Zobrist, 1994]" CLASS="XRef">
reference location</A>
]</P>
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