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17.8 <A NAME="13817">
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References</H1>
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Page numbers in brackets after a reference indicate its location in the chapter body.</P>
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Banerjee, P. 1994. <SPAN CLASS="BookTitle">
Parallel Algorithms for VLSI Computer-Aided Design Applications.</SPAN>
Englewood Cliffs, NJ: Prentice-Hall, 699 p. ISBN 0130158356. TK7874.75.B36. [<A HREF="CH17.7.htm#[Banerjee, 1994]" CLASS="XRef">
reference location</A>
]</P>
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Barke, E. 1988. “Line-to-ground capacitance calculation for VLSI: A comparison.” <SPAN CLASS="BookTitle">
IEEE Transactions on Computer-Aided Design,</SPAN>
Vol. 7, no. 2, pp. 295–298. Compares various equations for line to ground capacitance and finds the van der Meijs and Fokkema equation the most accurate. [<A HREF="CH17.6.htm#Barke88" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
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Black, J. R. 1969. “Electromigration failure modes in aluminum metallization for semiconductor devices.” <SPAN CLASS="BookTitle">
Proceedings of the IEEE,</SPAN>
Vol. 57, no. 9, pp. 1587–1594. Describes mechanism and theory of electromigration. Two failure modes are discussed: dissolution of silicon into aluminum, and condensation of aluminum vacancies to form voids. Electromigration failures in aluminum become important (less than 10 year lifetime) at current densities greater than 50 kA/sq.cm and temperatures greater than 150 °C. [<A HREF="CH17.7.htm#Black69" CLASS="XRef">
reference location</A>
]</P>
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Cadence. 1990. “Gate Ensemble User Guide.” Product Release 2.0. Describes gate-array place-and-route software. The algorithms for timing-driven placement are described in A. H. Chao, E. M. Nequist, and T. D. Vuong, “Direct solution of performance constraints during placement,” in <SPAN CLASS="BookTitle">
Proceedings of the IEEE Custom Integrated Circuits Conference,</SPAN>
1990. The delay models for timing analysis are described in “Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation,” in P. R. O’Brien and T. L. Savarino, in <SPAN CLASS="BookTitle">
Proceedings of the International Conference on Computer-Aided Design,</SPAN>
1989. [<A HREF="CH17.4.htm#Cadence90" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
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Cheng, C.-K., et al. 1992. “Geometric compaction on channel routing.” <SPAN CLASS="BookTitle">
IEEE Transactions on Computer-Aided Design,</SPAN>
Vol. 11, no. 1, pp. 115–127. [<A HREF="CH17.2.htm#Cheng92" CLASS="XRef">
</A>
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reference location</A>
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Chowdhury, S., and J. S. Barkatullah. 1988. “Current estimation in MOS IC logic circuits.” In <SPAN CLASS="BookTitle">
Proceedings of the International Conference on Computer-Aided Design.</SPAN>
Compares estimates for transient current flow for CMOS logic gates. Algebraic models give results close to SPICE simulations. The rest of the paper discusses the calculation of static current flow for nMOS logic gates. A model for static current for CMOS gates is developed in terms of the nMOS models.</P>
<P CLASS="Reference">
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D’Heurle, F. M. 1971. “Electromigration and failure in electronics: an introduction.” <SPAN CLASS="BookTitle">
Proceedings of the IEEE,</SPAN>
Vol. 59, no. 10, pp. 1409–1417. Describes the theory behind electromigration in bulk and thin-film metals. Includes some experimental results and reviews work by others. Describes the beneficial effects of adding copper to aluminum metallization. [<A HREF="CH17.7.htm#D'Heurle71" CLASS="XRef">
reference location</A>
]</P>
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Friedman, E. G. (Ed.). 1995. <SPAN CLASS="BookTitle">
Clock Distribution Networks in VLSI Circuits and Systems.</SPAN>
New York: IEEE Press, ISBN 0780310586. TK7874.75.C58. [<A HREF="CH17.7.htm#[Friedman, 1995]" CLASS="XRef">
reference location</A>
]</P>
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Gildenblat, G. S., and G. P. Schwartz (Eds.). 1991. <SPAN CLASS="BookTitle">
Metallization: Performance and Reliability Issues for VLSI and ULSI.</SPAN>
Bellingham, WA: SPIE, the International Society for Optical Engineering, 159 p. ISBN 0819407275. TK7874.M437. [<A HREF="CH17.7.htm#[Gildenblat and Schwartz, 1991]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
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Glendinning, W. B., and J. N. Helbert, (Eds.). 1991. <SPAN CLASS="BookTitle">
Handbook of VLSI Microlithography : Principles, Technology, and Applications.</SPAN>
Park Ridge, NJ: Noyes Publications, 649 p. ISBN 0815512813. TK7874.H3494. [<A HREF="CH17.7.htm#[Glendinning and Helbert, 1991]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
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Goel, A. K. 1994. <SPAN CLASS="BookTitle">
High Speed VLSI Interconnections: Modeling, Analysis, and Simulation. </SPAN>
New York: Wiley-Interscience, 622 p. ISBN 0471571229. TK7874.7.G63. 21 pages of references. [<A HREF="CH17.7.htm#[Goel, 1994]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
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Hashimoto, A., and J. Stevens. 1971. “Wire routing by optimal channel assignment within large apertures.” In <SPAN CLASS="BookTitle">
Proceedings of the 8th Design Automation Workshop,</SPAN>
pp. 155–169. [<A HREF="CH17.2.htm#Hashimoto71" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
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Hu, T. C., and E. S. Kuh (Eds.). 1983. <SPAN CLASS="BookTitle">
VLSI Circuit Layout: Theory and Design.</SPAN>
New York: IEEE Press. ISBN 0879421932. TK7874 .V5573. Contains 26 papers divided into six chapters; Part 1: Overview (a paper written for this book with 167 references on layout and routing); Part II: General; Part III: Wireability, Partitioning and Placement; Part IV: Routing; Part V: Layout Systems; Part VI: Module Generation. [<A HREF="CH17.7.htm#[Hu and Kuh, 1983]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
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Joobbani, R. 1986. <SPAN CLASS="BookTitle">
An Artificial Intelligence Approach to VLSI Routing.</SPAN>
Hingham, MA: Kluwer. ISBN 0-89838-205-X. TK7874.J663. Ph.D thesis on the development and testing of an intelligent router including an overview of the detailed routing problem and the Lee and “greedy” algorithms. [<A HREF="CH17.7.htm#Joobbani86" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
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Kahng, A. B., and G. Robins. 1995. <SPAN CLASS="BookTitle">
On Optimal Interconnections for VLSI.</SPAN>
Norwell, MA: Kluwer. ISBN 0-7923-9483-6. TK7874.75.K34. Extensive reference work on timing-driven detailed routing. [pp. 953, 956]</P>
<P CLASS="Reference">
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Lengauer, T. 1990. <SPAN CLASS="BookTitle">
Combinatorial Algorithms for Integrated Circuit Layout.</SPAN>
Chichester, England: Wiley. ISBN 0-471-92838-0. TK7874.L36. Background: Introduction to circuit layout; Optimization problems; Graph algorithms; Operations research and statistics. Combinatorial layout problems: The layout problem; Circuit partitioning; Placement, assignment, and floorplanning; Global routing and area routing; Detailed routing; Compaction. 484 references. [<A HREF="CH17.7.htm#Lengauer90" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=72534">
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Nakhla, M. S., and Q. J. Zhang (Eds.). 1994. <SPAN CLASS="BookTitle">
Modeling and Simulation of High Speed VLSI Interconnects.</SPAN>
Boston: Kluwer, 106 p. ISBN 0792394410. TK7874.75.M64. [<A HREF="CH17.7.htm#[Nakhla and Zhang, 1994]" CLASS="XRef">
reference location</A>
]</P>
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