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17.2 <A NAME="42292">
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Detailed Routing</H1>
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The global routing step determines the channels to be used for each interconnect. Using this information the detailed router decides the exact location and layers for each interconnect. <A HREF="CH17.2.htm#19897" CLASS="XRef">
Figure 17.9</A>
(a) shows typical metal rules. These rules determine the m1 <SPAN CLASS="Definition">
routing pitch</SPAN>
<A NAME="marker=35160">
</A>
(<A NAME="marker=35197">
</A>
<SPAN CLASS="Definition">
track pitch</SPAN>
, <A NAME="marker=36378">
</A>
<SPAN CLASS="Definition">
track spacing</SPAN>
, or just <SPAN CLASS="Definition">
pitch</SPAN>
<A NAME="marker=49831">
</A>
). We can set the m1 pitch to one of three values:</P>
<OL>
<LI CLASS="NumberFirst">
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<SPAN CLASS="Definition">
via-to-via</SPAN>
<A NAME="marker=35171">
</A>
(<SPAN CLASS="Definition">
VTV</SPAN>
<A NAME="marker=49808">
</A>
) pitch (or spacing), </LI>
<LI CLASS="NumberList">
<A NAME="pgfId=35117">
</A>
<SPAN CLASS="Definition">
via-to-line</SPAN>
<A NAME="marker=35172">
</A>
(<SPAN CLASS="Definition">
VTL</SPAN>
<A NAME="marker=49809">
</A>
or <SPAN CLASS="Definition">
line-to-via</SPAN>
<A NAME="marker=35174">
</A>
) pitch, or</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=35118">
</A>
<SPAN CLASS="Definition">
line-to-line</SPAN>
<A NAME="marker=51081">
</A>
(<SPAN CLASS="Definition">
LTL</SPAN>
<A NAME="marker=49810">
</A>
) pitch. </LI>
</OL>
<P CLASS="Body">
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The same choices apply to the m2 and other metal layers if they are present. Via-to-via spacing allows the router to place vias adjacent to each other. Via-to-line spacing is hard to use in practice because it restricts the router to nonadjacent vias. Using line-to-line spacing prevents the router from placing a via at all without using jogs and is rarely used. Via-to-via spacing is the easiest for a router to use and the most common. Using either via-to-line or via-to-via spacing means that the routing pitch is larger than the minimum metal pitch.</P>
<P CLASS="Body">
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Sometimes people draw a distinction between a cut and a via when they talk about large connections such as shown in <A HREF="CH17.2.htm#11355" CLASS="XRef">
Figure 17.10</A>
(a). We split or <A NAME="marker=42974">
</A>
<SPAN CLASS="Definition">
stitch</SPAN>
a large via into identically sized cuts (sometimes called a <A NAME="marker=42975">
</A>
<SPAN CLASS="Definition">
waffle via</SPAN>
<A NAME="marker=49834">
</A>
). Because of the profile of the metal in a contact and the way current flows into a contact, often the total resistance of several small cuts is less than that of one large cut. Using identically sized cuts also means the processing conditions during contact etching, which may vary with the area and perimeter of a contact, are the same for every cut on the chip.</P>
<P CLASS="Body">
<A NAME="pgfId=77080">
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In a <A NAME="marker=77079">
</A>
<SPAN CLASS="Definition">
stacked via </SPAN>
the contact cuts all overlap in a layout plot and it is impossible to tell just how many vias on which layers are present. <A HREF="CH17.2.htm#11355" CLASS="XRef">
Figure 17.10</A>
(b–f) show an alternative way to draw <A NAME="marker=77085">
</A>
contacts and <A NAME="marker=77086">
</A>
vias. Though this is not a standard, using the diagonal box convention makes it possible to recognize stacked vias and contacts on a layout (in any orientation). I shall use these conventions when it is necessary.</P>
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<IMG SRC="CH17-9.gif" ALIGN="BASELINE">
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FIGURE 17.9 <A NAME="19897">
</A>
The metal routing pitch. (a) An example of <SPAN CLASS="Symbol">
l</SPAN>
-based metal design rules for m1 and via1 (m1/m2 via). (b) Via-to-via pitch for adjacent vias. (c) Via-to-line (or line-to-via) pitch for nonadjacent vias. (d) Line-to-line pitch with no vias.</P>
</TD>
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</TABLE>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=77102">
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</P>
<DIV>
<IMG SRC="CH17-10.gif">
</DIV>
</TD>
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<P CLASS="TableFigureTitle">
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FIGURE 17.10 <A NAME="11355">
</A>
(a) A large m1 to m2 via. The black squares represent the holes (or cuts) that are etched in the insulating material between the m1 and 2 layers. (b) A m1 to m2 via (a via1). (c) A contact from m1 to diffusion or polysilicon (a contact). (d) A via1 placed over (or stacked over) a contact. (e) A m2 to m3 via (a via2) (f) A via2 stacked over a via1 stacked over a contact. Notice that the black square in parts b–c do <SPAN CLASS="Emphasis">
not</SPAN>
represent the actual location of the cuts. The black squares are offset so you can recognize stacked vias and contacts.</P>
</TD>
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</TABLE>
<P CLASS="Body">
<A NAME="pgfId=5764">
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In a two-level metal CMOS ASIC technology we complete the wiring using the two different metal layers for the horizontal and vertical directions, one layer for each direction. This is <A NAME="marker=5765">
</A>
<SPAN CLASS="Definition">
Manhattan routing</SPAN>
, because the results look similar to the rectangular north–south and east–west layout of streets in New York City. Thus, for example, if terminals are on the m2 layer, then we route the horizontal branches in a channel using m2 and the vertical trunks using m1. <A HREF="CH17.2.htm#10346" CLASS="XRef">
Figure 17.11</A>
shows that, although we may choose a <SPAN CLASS="Definition">
preferred direction</SPAN>
<A NAME="marker=5838">
</A>
for each metal layer (for example, m1 for horizontal routing and m2 for vertical routing), this may lead to problems in cases that have both horizontal and vertical channels. In these cases we define a <SPAN CLASS="Definition">
preferred metal layer</SPAN>
<A NAME="marker=67723">
</A>
in the direction of the channel spine. In <A HREF="CH17.2.htm#10346" CLASS="XRef">
Figure 17.11</A>
, because the logic cell connectors are on m2, any vertical channel has to use vias at every logic cell location. By changing the orientation of the metal directions in vertical channels, we can avoid this, and instead we only need to place vias at the intersection of horizontal and vertical channels. </P>
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<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=5847">
</A>
</P>
<DIV>
<IMG SRC="CH17-11.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=5853">
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FIGURE 17.11 <A NAME="10346">
</A>
An expanded view of part of a cell-based ASIC. (a) Both channel 4 and channel 5 use m1 in the horizontal direction and m2 in the vertical direction. If the logic cell connectors are on m2 this requires vias to be placed at every logic cell connector in channel 4. (b) Channel 4 and 5 are routed with m1 along the direction of the channel spine (the long direction of the channel). Now vias are required only for nets 1 and 2, at the intersection of the channels.</P>
</TD>
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</TABLE>
<P CLASS="Body">
<A NAME="pgfId=5866">
</A>
<A HREF="CH17.2.htm#14305" CLASS="XRef">
Figure 17.12</A>
shows an imaginary logic cell with connectors. Double-entry logic cells intended for two-level metal routing have connectors at the top and bottom of the logic cell, usually in m2. Logic cells intended for processes with three or more levels of metal have connectors in the center of the cell, again usually on m2. Logic cells may use both m1 and m2 internally, but the use of m2 is usually minimized. The router normally uses a simplified view of the logic cell called a <SPAN CLASS="Definition">
phantom</SPAN>
<A NAME="marker=50609">
</A>
. The phantom contains only the logic cell information that the router needs: the connector locations, types, and names; the abutment and bounding boxes; enough layer information to be able to place cells without violating design rules; and a <SPAN CLASS="Definition">
blockage map</SPAN>
<A NAME="marker=50620">
</A>
—the locations of any metal inside the cell that blocks routing.</P>
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<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=5862">
</A>
<IMG SRC="CH17-12.gif" ALIGN="BASELINE">
</P>
</TD>
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<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=5865">
</A>
FIGURE 17.12 <A NAME="14305">
</A>
The different types of connections that can be made to a cell. This cell has connectors at the top and bottom of the cell (normal for cells intended for use with a two-level metal process) and internal connectors (normal for logic cells intended for use with a three-level metal process). The interconnect and connections are drawn to scale.</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=42536">
</A>
<A HREF="CH17.2.htm#31067" CLASS="XRef">
Figure 17.13</A>
illustrates some terms used in the detailed routing of a channel. The channel spine in <A HREF="CH17.2.htm#31067" CLASS="XRef">
Figure 17.13</A>
is horizontal with terminals at the top and the bottom, but a channel can also be vertical. In either case terminals are spaced along the longest edges of the channel at given, fixed locations. Terminals are usually located on a grid defined by the routing pitch on that layer (we say terminals are either <SPAN CLASS="Definition">
on-grid</SPAN>
<A NAME="marker=49916">
</A>
or <SPAN CLASS="Definition">
off-grid</SPAN>
<A NAME="marker=49917">
</A>
). We make connections between terminals using interconnects that consist of one or more <A NAME="marker=42540">
</A>
<SPAN CLASS="Definition">
trunks</SPAN>
running parallel to the length of the channel and <A NAME="marker=42541">
</A>
<SPAN CLASS="Definition">
branches</SPAN>
that connect the trunk to the terminals. If more than one trunk is used, the trunks are connected by <A NAME="marker=42542">
</A>
<SPAN CLASS="Definition">
doglegs</SPAN>
. Connections exit the channel at <SPAN CLASS="Definition">
pseudoterminals</SPAN>
<A NAME="marker=71681">
</A>
. </P>
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<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=42548">
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<IMG SRC="CH17-13.gif" ALIGN="BASELINE">
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</TD>
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<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=42550">
</A>
FIGURE 17.13 <A NAME="31067">
</A>
Terms used in channel routing. (a) A channel with four horizontal tracks. (b) An expanded view of the left-hand portion of the channel showing (approximately to scale) how the m1 and m2 layers connect to the logic cells on either side of the channel. (c) The construction of a via1 (m1/m2 via).</P>
</TD>
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</TABLE>
<P CLASS="Body">
<A NAME="pgfId=42554">
</A>
The trunk and branch connections run in <A NAME="marker=42553">
</A>
<SPAN CLASS="Definition">
tracks</SPAN>
(equispaced, like railway tracks). If the trunk connections use m1, the <SPAN CLASS="Definition">
horizontal track spacing</SPAN>
<A NAME="marker=42555">
</A>
(usually just called the <SPAN CLASS="Definition">
track spacing</SPAN>
<A NAME="marker=42556">
</A>
for channel routing) is equal to the m1 routing pitch. The maximum number of interconnects we need in a channel multiplied by the horizontal track spacing gives the minimum height of a channel (see <A HREF="CH17.2.htm#32630" CLASS="XRef">
Section 17.2.2</A>
on how to determine the maximum number of interconnects needed). Each terminal occupies a <A NAME="marker=42560">
</A>
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