ch17.3.htm

介绍asci设计的一本书

m</SPAN>
m three-level metal CMOS process, <A NAME="marker=72124">
 </A>
G5. The limit of 1 mA of current per square micron of metal cross section is a good rule-of-thumb to follow for current density in aluminum-based interconnect.</P>
<P CLASS="Body">
<A NAME="pgfId=25323">
 </A>
Some CMOS processes also have <SPAN CLASS="Definition">
maximum metal-width rules</SPAN>
<A NAME="marker=25405">
 </A>
 (or <SPAN CLASS="Definition">
fat-metal rules</SPAN>
). This is because <A NAME="marker=25406">
 </A>
stress (especially at the corners of the die, which occurs during <SPAN CLASS="Definition">
die attach</SPAN>
<A NAME="marker=29052">
 </A>
&#8212;mounting the die on the chip carrier) can cause large metal areas to lift. A solution to this problem is to place slots in the wide metal lines. These rules are dependent on the ASIC vendor&#8217;s level of experience.</P>
<P CLASS="Body">
<A NAME="pgfId=48979">
 </A>
To determine the power-bus widths we need to determine the bus currents. The largest problem is emulating the system&#8217;s operating conditions. Input vectors to test the system are not necessarily representative of actual system operation. Clock-bus sizing depends strongly on the parameter <SPAN CLASS="EquationNumber">
k</SPAN>
<SUB CLASS="Subscript">
AC/DC</SUB>
 in Eq. <A HREF="CH17.3.htm#41231" CLASS="XRef">
17.10</A>
, since the clock spine carries alternating current. (For the sources of power dissipation in CMOS, see Section&nbsp;15.5, &#8220;Power Dissipation.&#8221;)</P>
<P CLASS="Body">
<A NAME="pgfId=29421">
 </A>
Gate arrays normally use a regular <SPAN CLASS="Definition">
power grid</SPAN>
<A NAME="marker=33737">
 </A>
 as part of the gate-array base. The gate-array logic cells contain two fixed-width power buses inside the cell, running horizontally on m1. The horizontal m1 power buses are then strapped in a vertical direction by m2 buses, which run vertically across the chip. The resistance of the power grid is extracted and simulated with SPICE during the base-array design to model the effects of IR drops under worst-case conditions.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="4">
<P CLASS="TableTitle">
<A NAME="pgfId=76726">
 </A>
TABLE&nbsp;17.1&nbsp;<A NAME="28224">
 </A>
Metallization reliability rules for a typical 0.5 micron ( l = 0.25<SPAN CLASS="Symbol">
m</SPAN>
m) CMOS process.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=76735">
 </A>
<SPAN CLASS="TableHeads">
Layer/contact/via</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=76740">
 </A>
<SPAN CLASS="TableHeads">
Current limit<A HREF="#pgfId=76739" CLASS="footnote">
1</A>
</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=76745">
 </A>
<SPAN CLASS="TableHeads">
Metal thickness<A HREF="#pgfId=76744" CLASS="footnote">
2</A>
</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=76750">
 </A>
<SPAN CLASS="TableHeads">
Resistance<A HREF="#pgfId=76749" CLASS="footnote">
3</A>
</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=76752">
 </A>
m1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76754">
 </A>
1 mA <SPAN CLASS="Symbol">
m</SPAN>
m<SUP CLASS="Superscript">
&#8211;1</SUP>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76756">
 </A>
7000 &Aring;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76758">
 </A>
95 m<SPAN CLASS="Symbol">
W</SPAN>
/square</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=76760">
 </A>
m2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76762">
 </A>
1 mA <SPAN CLASS="Symbol">
m</SPAN>
m<SUP CLASS="Superscript">
&#8211;1</SUP>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76764">
 </A>
7000 &Aring;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76766">
 </A>
95 m<SPAN CLASS="Symbol">
W</SPAN>
/square</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=76768">
 </A>
m3</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76770">
 </A>
2  mA <SPAN CLASS="Symbol">
m</SPAN>
m<SUP CLASS="Superscript">
&#8211;1</SUP>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76772">
 </A>
12,000 &Aring;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76774">
 </A>
48 m<SPAN CLASS="Symbol">
W</SPAN>
/square</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=76776">
 </A>
0.8 <SPAN CLASS="Symbol">
m</SPAN>
m square m1 contact to diffusion</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76778">
 </A>
0.7  mA</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76780">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76782">
 </A>
11 <SPAN CLASS="Symbol">
W</SPAN>
 </P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=76784">
 </A>
0.8 <SPAN CLASS="Symbol">
m</SPAN>
m square m1 contact to poly</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76786">
 </A>
0.7 mA</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76788">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76790">
 </A>
16 <SPAN CLASS="Symbol">
W</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=76792">
 </A>
0.8 <SPAN CLASS="Symbol">
m</SPAN>
m square m1/m2 via (via1)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76794">
 </A>
0.7 mA</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76796">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76798">
 </A>
3.6 <SPAN CLASS="Symbol">
W</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=76800">
 </A>
0.8 <SPAN CLASS="Symbol">
m</SPAN>
m square m2/m3 via (via2)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76802">
 </A>
0.7 mA</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76804">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76806">
 </A>
3.6 <SPAN CLASS="Symbol">
W</SPAN>
</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=67677">
 </A>
Standard cells are constructed in a similar fashion to gate-array cells, with power buses running horizontally in m1 at the top and bottom of each cell. A row of standard cells uses <SPAN CLASS="Definition">
end-cap cells</SPAN>
<A NAME="marker=67678">
 </A>
 that connect to the VDD and VSS power buses placed by the power router. Power routing of cell-based ASICs may include the option to include vertical m2 straps at a specified intervals. Alternatively the number of standard cells that can be placed in a row may be limited during placement. The power router forms an interdigitated comb structure, minimizing the number of times a VDD or VSS power bus needs to change layers. This is achieved by routing with a <SPAN CLASS="Definition">
routing bias</SPAN>
<A NAME="marker=67679">
 </A>
 on preferred layers. For example, VDD may be routed with a left-and-down bias on m1, with VSS routed using right-and-up bias on m2. </P>
<P CLASS="Body">
<A NAME="pgfId=67680">
 </A>
Three-level metal processes either use a m3 with a thickness and pitch that is comparable to m1 and m2 (which usually have approximately the same thickness and pitch) or they use metal that is much thicker (up to twice as thick as m1 and m2) with a coarser pitch (up to twice as wide as m1 and m2). The factor that determines the m3/4/5 properties is normally the sophistication of the fabrication process.</P>
<P CLASS="Body">
<A NAME="pgfId=35705">
 </A>
In a three-level metal process, power routing is similar to two-level metal ASICs. Power buses inside the logic cells are still normally run on m1. Using HVH routing it would be possible to run the power buses on m3 and drop vias all the way down to m1 when power is required in the cells. The problem with this approach is that it creates pillars of blockage across all three layers.</P>
<P CLASS="Body">
<A NAME="pgfId=33973">
 </A>
Using three or more layers of metal for routing, it is possible to eliminate some of the channels completely. In these cases we complete all the routing in m2 and m3 on top of the logic cells using connectors placed in the center of the cells on m1. If we can eliminate the channels between cell rows, we can flip rows about a horizontal axis and abut adjacent rows together (a technique known as <SPAN CLASS="Definition">
flip and abut</SPAN>
<A NAME="marker=33974">
 </A>
). If the power buses are at the top (VDD) and bottom (VSS) of the cells in m1 we can abut or overlap the power buses (joining VDD to VDD and VSS to VSS in alternate rows).</P>
<P CLASS="Body">
<A NAME="pgfId=16962">
 </A>
Power distribution schemes are also a function of process and packaging technology. Recall that flip-chip technology allows pads to be placed anywhere on a chip (see Section&nbsp;16.1.5, &#8220;I/O and Power Planning,&#8221; especially Figure&nbsp;16.13d). Four-level metal and aggressive stacked-via rules allow I/O pad circuits to be placed in the core. The problems with this approach include placing the ESD and latch-up protection circuits required in the I/O pads (normally kept widely separated from core logic) adjacent to the logic cells in the core.</P>
</DIV>
<HR>
<DIV CLASS="footnotes">
<DIV CLASS="footnote">
<P CLASS="TableFootnote">
<SPAN CLASS="footnoteNumber">
1.</SPAN>
<A NAME="pgfId=76739">
 </A>
 At 125 &#176;C for unidirectional current. Limits for 110 &#176;C are <SPAN CLASS="Symbol">
&#165;</SPAN>
 1.5 higher. Limits for 85 &#176;C are <SPAN CLASS="Symbol">
&#165;</SPAN>
 3 higher. Current limits for bidirectional current are <SPAN CLASS="Symbol">
&#165;</SPAN>
 1.5 higher than the unidirectional limits.</P>
</DIV>
<DIV CLASS="footnote">
<P CLASS="TableFootnote">
<SPAN CLASS="footnoteNumber">
2.</SPAN>
<A NAME="pgfId=76744">
 </A>
10,000 &Aring; (ten thousand angstroms) = 1 <SPAN CLASS="Symbol">
m</SPAN>
m.</P>
</DIV>
<DIV CLASS="footnote">
<P CLASS="TableFootLast">
<SPAN CLASS="footnoteNumber">
3.</SPAN>
<A NAME="pgfId=76749">
 </A>
Worst case at 110 &#176;C.</P>
</DIV>
</DIV>
<HR><P>[&nbsp;<A HREF="CH17.htm">Chapter&nbsp;start</A>&nbsp;]&nbsp;[&nbsp;<A HREF="CH17.2.htm">Previous&nbsp;page</A>&nbsp;]&nbsp;[&nbsp;<A HREF="CH17.4.htm">Next&nbsp;page</A>&nbsp;]</P></BODY>

<!--#include file="Copyright.html"--><!--#include file="footer.html"-->