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<TITLE> 17.3 Special Routing</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
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17.3 <A NAME="11266">
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Special Routing</H1>
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The routing of nets that require special attention, clock and power nets for example, is normally done before detailed routing of signal nets. The architecture and structure of these nets is performed as part of floorplanning, but the sizing and topology of these nets is finalized as part of the routing step.</P>
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17.3.1 <A NAME="25512">
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Clock Routing</H2>
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Gate arrays normally use a clock spine (a regular grid), eliminating the need for special routing (see Section 16.1.6, “Clock Planning”). The clock distribution grid is designed at the same time as the gate-array base to ensure a minimum clock skew and minimum clock latency—given power dissipation and clock buffer area limitations. Cell-based ASICs may use either a clock spine, a clock tree, or a hybrid approach. <A HREF="CH17.3.htm#26823" CLASS="XRef">
Figure 17.21</A>
shows how a clock router may minimize clock skew in a clock spine by making the path lengths, and thus net delays, to every leaf node equal—using jogs in the interconnect paths if necessary. More sophisticated clock routers perform <SPAN CLASS="Definition">
clock-tree synthesis</SPAN>
<A NAME="marker=35472">
</A>
(automatically choosing the depth and structure of the clock tree) and <SPAN CLASS="Definition">
clock-buffer insertion</SPAN>
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(equalizing the delay to the leaf nodes by balancing interconnect delays and buffer delays).</P>
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<IMG SRC="CH17-21.gif" ALIGN="BASELINE">
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FIGURE 17.21 <A NAME="26823">
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Clock routing. (a) A clock network for the cell-based ASIC from Figure 16.11. (b) Equalizing the interconnect segments between CLK and all destinations (by including jogs if necessary) minimizes clock skew.</P>
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The clock tree may contain multiply-driven nodes (more than one active element driving a net). The net delay models that we have used break down in this case and we may have to extract the clock network and perform circuit simulation, followed by back-annotation of the clock delays to the netlist (for circuit extraction, see <A HREF="CH17.4.htm#11650" CLASS="XRef">
Section 17.4</A>
) and the bus currents to the clock router. The sizes of the clock buses depend on the current they must carry. The limits are set by reliability issues to be discussed next.</P>
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Clock skew induced by hot-electron wearout was mentioned in Section 16.1.6, “Clock Planning.” Another factor contributing to unpredictable clock skew is changes in clock-buffer delays with variations in power-supply voltage due to data-dependent activity. This <SPAN CLASS="Definition">
activity-induced clock skew</SPAN>
<A NAME="marker=50677">
</A>
can easily be larger than the skew achievable using a clock router. For example, there is little point in using software capable of reducing clock skew to less than 100 ps if, due to fluctuations in power-supply voltage when part of the chip becomes active, the clock-network delays change by 200 ps.</P>
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The power buses supplying the buffers driving the clock spine carry direct current (<A NAME="marker=72122">
</A>
unidirectional current or DC), but the clock spine itself carries alternating current (<A NAME="marker=72123">
</A>
bidirectional current or AC). The difference between <SPAN CLASS="Emphasis">
electromigration</SPAN>
failure rates due to AC and DC leads to different rules for sizing clock buses. As we explained in Section 16.1.6, “Clock Planning,” the fastest way to drive a large load in CMOS is to taper successive stages by approximately <SPAN CLASS="EquationVariables">
e</SPAN>
<SPAN CLASS="Symbol">
ª</SPAN>
3. This is not necessarily the smallest-area or lowest-power approach, however [<A NAME="Veendrick84">
</A>
Veendrick, 1984].</P>
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17.3.2 <A NAME="23204">
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Power Routing</H2>
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Each of the power buses has to be <SPAN CLASS="Definition">
sized</SPAN>
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</A>
according to the current it will carry. Too much current in a power bus can lead to a failure through a mechanism known as <SPAN CLASS="Definition">
electromigration</SPAN>
<A NAME="marker=17105">
</A>
<A NAME="[Young and Christou, 1994]">
</A>
[Young and Christou, 1994]. The required power-bus widths can be estimated automatically from library information, from a separate <SPAN CLASS="Definition">
power simulation</SPAN>
<A NAME="marker=17115">
</A>
tool, or by entering the <A NAME="marker=17116">
</A>
power-bus widths to the routing software by hand. Many routers use a default power-bus width so that it is quite easy to complete routing of an ASIC without even knowing about this problem.</P>
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For a <A NAME="marker=37535">
</A>
direct current (<A NAME="marker=37532">
</A>
<A NAME="marker=37533">
</A>
<A NAME="marker=39145">
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DC) the <SPAN CLASS="Definition">
mean time to failure</SPAN>
<A NAME="marker=37531">
</A>
(<A NAME="marker=37526">
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<A NAME="marker=37527">
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<A NAME="marker=39143">
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MTTF) due to electromigration is experimentally found to obey the following equation: </P>
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MTTF</P>
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<A NAME="pgfId=84421">
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=</P>
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<P CLASS="TableEqnLeft">
<A NAME="pgfId=84423">
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<SPAN CLASS="EquationNumber">
A</SPAN>
<SPAN CLASS="EquationVariables">
J</SPAN>
<SUP CLASS="Superscript">
–2</SUP>
<SPAN CLASS="EquationNumber">
exp</SPAN>
–<SPAN CLASS="EquationVariables">
E</SPAN>
/<SPAN CLASS="EquationNumber">
k</SPAN>
<SPAN CLASS="EquationVariables">
T</SPAN>
,</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnLeft">
<A NAME="pgfId=84425">
</A>
<SPAN CLASS="Symbol">
</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=84427">
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<A NAME="14020">
</A>
(17.9)</P>
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</TABLE>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=25171">
</A>
where <SPAN CLASS="EquationVariables">
J</SPAN>
is the current density; <SPAN CLASS="EquationVariables">
E</SPAN>
is approximately 0.5 eV; <SPAN CLASS="EquationNumber">
k</SPAN>
, Boltzmann’s constant, is 8.62 <SPAN CLASS="Symbol">
¥</SPAN>
10<SUP CLASS="Superscript">
–5</SUP>
eVK<SUP CLASS="Superscript">
–1</SUP>
; and <SPAN CLASS="EquationVariables">
T</SPAN>
is absolute temperature in kelvins. </P>
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There are a number of different approaches to model the effect of an AC component. A typical expression is </P>
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</P>
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<P CLASS="TableEqnCenter">
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</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=84557">
</A>
<SPAN CLASS="EquationNumber">
A</SPAN>
<SPAN CLASS="EquationVariables">
J</SPAN>
<SUP CLASS="Superscript">
–2</SUP>
<SPAN CLASS="EquationNumber">
exp</SPAN>
–<SPAN CLASS="EquationVariables">
E</SPAN>
/<SPAN CLASS="EquationNumber">
k</SPAN>
<SPAN CLASS="EquationVariables">
T</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnLeft">
<A NAME="pgfId=84559">
</A>
<SPAN CLASS="Symbol">
</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqn">
<A NAME="pgfId=84561">
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</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnRight">
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MTTF</P>
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<P CLASS="TableEqnCenter">
<A NAME="pgfId=84565">
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=</P>
</TD>
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–––––––––––––––––––––––––</P>
</TD>
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<P CLASS="TableEqnLeft">
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,</P>
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<P CLASS="TableEqnNumber">
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<A NAME="41231">
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(17.10)</P>
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</P>
</TD>
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<P CLASS="TableEqnCenter">
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</P>
</TD>
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<P CLASS="TableEqnCenter">
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<SPAN CLASS="OverlineVariables">
J</SPAN>
<SPAN CLASS="Overline">
| </SPAN>
<SPAN CLASS="OverlineVariables">
J</SPAN>
<SPAN CLASS="Overline">
|</SPAN>
+ k<SUB CLASS="Subscript">
AC/DC</SUB>
<SPAN CLASS="Overline">
| </SPAN>
<SPAN CLASS="OverlineVariables">
J</SPAN>
<SPAN CLASS="Overline">
|</SPAN>
<SUP CLASS="Superscript">
2</SUP>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnLeft">
<A NAME="pgfId=84579">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqn">
<A NAME="pgfId=84581">
</A>
</P>
</TD>
</TR>
</TABLE>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=25182">
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where <SPAN CLASS="Overline">
J</SPAN>
is the average of <SPAN CLASS="EquationVariables">
J(t)</SPAN>
, and <SPAN CLASS="Overline">
| </SPAN>
<SPAN CLASS="OverlineVariables">
J</SPAN>
<SPAN CLASS="Overline">
|</SPAN>
is the average of | J |. The constant <SPAN CLASS="EquationNumber">
k</SPAN>
<SUB CLASS="Subscript">
AC/DC</SUB>
relates the relative effects of AC and DC and is typically between 0.01 and 0.0001. Electromigration problems become serious with a MTTF of less than 10<SUP CLASS="Superscript">
5</SUP>
hours (approximately 10 years) for current densities (DC) greater than 0.5 GAm<SUP CLASS="Superscript">
–2</SUP>
at temperatures above 150 °C.</P>
<P CLASS="Body">
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<A HREF="CH17.3.htm#28224" CLASS="XRef">
Table 17.1</A>
lists example <SPAN CLASS="Definition">
metallization reliability rules</SPAN>
<A NAME="marker=25232">
</A>
—limits for the current you can pass through a metal layer, contact, or via—for the typical 0.5 <SPAN CLASS="Symbol">
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