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<H1 CLASS="Heading1">
<A NAME="pgfId=1331">
</A>
17.6 <A NAME="30558">
</A>
Problems</H1>
<P CLASS="Exercise">
<A NAME="pgfId=51092">
</A>
*=Difficult, **=Very difficult, *** = Extremely difficult</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=16858">
</A>
17.1 (Routing measures, 20 min.). Channel density is a useful measure, but with the availability of more than two layers of metal, area-based maze routers are becoming more common. Lyle Smith, in his 1983 Stanford Ph.D. thesis, defines the <SPAN CLASS="Definition">
Manhattan area measure</SPAN>
<A NAME="marker=16877">
</A>
(<A NAME="marker=16878">
</A>
MAM) as: </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnRight">
<A NAME="pgfId=84941">
</A>
MAM</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=84943">
</A>
=</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnLeft">
<A NAME="pgfId=84945">
</A>
area needed/area available.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=84947">
</A>
(17.11)</P>
</TD>
</TR>
</TABLE>
<P CLASS="ExerciseNoIndent">
<A NAME="pgfId=16865">
</A>
where you calculate the area needed by assuming routing on a single layer and ignore any interconnect overlaps. Calculate the MAM for <A HREF="CH17.2.htm#31065" CLASS="XRef">
Figure 17.14</A>
. Once the MAM reaches 0.5, most two-layer routers have difficulty.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=6176">
</A>
17.2 (*Benchmarking routers, 30 min.) Your design team needs a new router to complete your ASIC project. Your boss puts you in charge of benchmarking. She wants a list of the items you will test, and a description of how you will test them. </P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=6217">
</A>
17.3 (Timing-driven routing) <SPAN CLASS="Bold">
(a)</SPAN>
Calculate the delay from A to C in <A HREF="CH17.1.htm#28148" CLASS="XRef">
Figure 17.3</A>
(b) if the wire between <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="Subscript">
3</SUB>
and <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="Subscript">
4</SUB>
is increased to 5 mm. <SPAN CLASS="Bold">
(b)</SPAN>
If you want to measure the delay to the 90 percent point, what is the skew in signal arrival time between inverters B and C? <SPAN CLASS="Bold">
(c)</SPAN>
If you use the Elmore constant to characterize the delay between inverter A and inverter C as an RC element, what is the delay (measured to the 50 percent trip point) if you replace the step function at the output of inverter A with a linear ramp with a fall time of 0.1 ns?</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=71348">
</A>
17.4 (Elmore delay, 30 min.) Recalculate <SPAN CLASS="Symbol">
t</SPAN>
<SUB CLASS="SubscriptVariable">
D</SUB>
<SUB CLASS="Subscript">
4</SUB>
, <SPAN CLASS="Symbol">
t</SPAN>
<SUB CLASS="SubscriptVariable">
D</SUB>
<SUB CLASS="Subscript">
2</SUB>
, and <SPAN CLASS="Symbol">
t</SPAN>
<SUB CLASS="SubscriptVariable">
D</SUB>
<SUB CLASS="Subscript">
4</SUB>
– <SPAN CLASS="Symbol">
t</SPAN>
<SUB CLASS="SubscriptVariable">
D</SUB>
<SUB CLASS="Subscript">
2</SUB>
for the example in <A HREF="CH17.1.htm#20690" CLASS="XRef">
Section 17.1.2</A>
neglecting the pull-down resistance <SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
pd</SUB>
and comment on your answers.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=71346">
</A>
17.5 (Clock routing, 30 min.) Design a clock distribution system with minimum latency given the following specifications: The clocked elements are distributed randomly, but uniformly across the chip. The chip is 400 mil per side. There are 16,000 flip-flops to clock; each flip-flop clock input presents a load of 0.02 pF (one standard load). There are four different types of inverting buffer available (typical for a 0.5 <SPAN CLASS="Symbol">
m</SPAN>
m process):</P>
<P CLASS="Exercise">
<A NAME="pgfId=70981">
</A>
1X buffer: <SPAN CLASS="EquationVariables">
T</SPAN>
<SUB CLASS="SubscriptVariable">
D</SUB>
= 0.1 + 1.5 <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
L</SUB>
ns; 4X buffer: <SPAN CLASS="EquationVariables">
T</SPAN>
<SUB CLASS="SubscriptVariable">
D</SUB>
= 0.3 + 0.55 <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
L</SUB>
ns;</P>
<P CLASS="Exercise">
<A NAME="pgfId=70982">
</A>
8X buffer: <SPAN CLASS="EquationVariables">
T</SPAN>
<SUB CLASS="SubscriptVariable">
D</SUB>
= 0.5 + 0.25 <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
L</SUB>
ns; 32X buffer: <SPAN CLASS="EquationVariables">
T</SPAN>
<SUB CLASS="SubscriptVariable">
D</SUB>
= 2 + 0.004 <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
L</SUB>
ns.</P>
<P CLASS="ExerciseNoIndent">
<A NAME="pgfId=23192">
</A>
In these equations <SPAN CLASS="EquationVariables">
T</SPAN>
<SUB CLASS="SubscriptVariable">
D</SUB>
is the buffer delay (assume rise and fall times are approximately equal) and <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
L</SUB>
is the buffer load expressed in standard loads. Electromigration limits require a limit of 1 mA (DC) per micron metal width or 10 mA per micron for AC signals with no DC component. No metal bus may be wider than 100 <SPAN CLASS="Symbol">
m</SPAN>
m. The m2 line capacitance is 0.015 f F<SPAN CLASS="Symbol">
m</SPAN>
m<SUP CLASS="Superscript">
–2</SUP>
(area) and 0.035 f F<SPAN CLASS="Symbol">
m</SPAN>
m<SUP CLASS="Superscript">
–1</SUP>
(fringing).</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=6219">
</A>
17.6 (Power and ground routing, 10 min.) Calculate the parallel-plate capacitance between a VDD power ring routed on m2 and an identical VSS ring routed on m1 directly underneath. The chip is 500 mil on a side; assume the power ring runs around the edge of the chip. The VDD and VSS bus are capable of carrying 0.5 A and are both 500 <SPAN CLASS="Symbol">
m</SPAN>
m wide. Assume that m1 and m2 are separated by a SiO<SUB CLASS="Subscript">
2</SUB>
dielectric 10,000 Å thick. This capacitance can actually be used for decoupling supplies.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=6220">
</A>
17.7 <A NAME="11042">
</A>
(Overlap capacitance, 10 min.) Consider two interconnects, both of width <SPAN CLASS="EquationVariables">
W</SPAN>
, separated by a layer of SiO<SUB CLASS="Subscript">
2</SUB>
of thickness T, and that overlap for a distance L.</P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=6251">
</A>
a. What is the overlap capacitance, assuming there are no fringing effects? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=6252">
</A>
b. Calculate the overlap capacitance if <SPAN CLASS="EquationVariables">
W</SPAN>
= 1 <SPAN CLASS="Symbol">
m</SPAN>
m, <SPAN CLASS="EquationVariables">
T</SPAN>
= 0.5 <SPAN CLASS="Symbol">
m</SPAN>
m, for <SPAN CLASS="EquationVariables">
L</SPAN>
= 1, 10, and 100 <SPAN CLASS="Symbol">
m</SPAN>
m.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=6253">
</A>
c. Calculate the gate capacitance of an <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor with transistor size <SPAN CLASS="EquationVariables">
W</SPAN>
/<SPAN CLASS="EquationVariables">
L</SPAN>
= 2/1 (that is, <SPAN CLASS="EquationVariables">
W</SPAN>
= 2 <SPAN CLASS="Symbol">
m</SPAN>
m, <SPAN CLASS="EquationVariables">
L</SPAN>
= 1 <SPAN CLASS="Symbol">
m</SPAN>
m), with a gate oxide thickness of 200 Å (again assuming no fringing effects).</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=6260">
</A>
d. Comment on your answers.</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=34709">
</A>
17.8 (Standard load, 10 min.) Calculate the size of a standard load for the 1 <SPAN CLASS="Symbol">
m</SPAN>
m process with the parasitic capacitance values shown in <A HREF="CH17.4.htm#19399" CLASS="XRef">
Table 17.2</A>
. Assume the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel and <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel devices in a two-input NAND gate are all 10/1 with minimum length.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=34720">
</A>
17.9 <A NAME="36568">
</A>
(Fringing capacitance, 45 min) You can calculate the capacitance per unit length (including fringing capacitance) of an interconnect with rectangular cross section (width <SPAN CLASS="EquationVariables">
W</SPAN>
, thickness <SPAN CLASS="EquationVariables">
T</SPAN>
, and a distance <SPAN CLASS="EquationVariables">
H</SPAN>
above a ground plane) from the approximate formula (from [<A NAME="Barke88">
</A>
Barke, 1988]—the equation was originally proposed by van der Meijs and Fokkema): </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnRight">
<A NAME="pgfId=84674">
</A>
<SPAN CLASS="EquationVariables">
C</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=84676">
</A>
=</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnLeft">
<A NAME="pgfId=84678">
</A>
<SPAN CLASS="Symbol">
e</SPAN>
[(<SPAN CLASS="EquationVariables">
W</SPAN>
/<SPAN CLASS="EquationVariables">
H</SPAN>
) + 1.064 <SPAN CLASS="Symbol">
÷</SPAN>
(<SPAN CLASS="EquationVariables">
W</SPAN>
/<SPAN CLASS="EquationVariables">
H</SPAN>
) + 1.06 <SPAN CLASS="Symbol">
÷</SPAN>
(<SPAN CLASS="EquationVariables">
T</SPAN>
/<SPAN CLASS="EquationVariables">
H</SPAN>
) + 0.77]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnLeft">
<A NAME="pgfId=84680">
</A>
,</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=84682">
</A>
(17.12)</P>
</TD>
</TR>
</TABLE>
<P CLASS="Exercise">
<A NAME="pgfId=15061">
</A>
where <SPAN CLASS="Symbol">
e = e</SPAN>
<SUB CLASS="Subscript">
r </SUB>
<SPAN CLASS="Symbol">
e</SPAN>
<SUB CLASS="Subscript">
0</SUB>
is the dielectric constant of the insulator surrounding the interconnect. The relative permittivity of a SiO<SUB CLASS="Subscript">
2</SUB>
dielectric <SPAN CLASS="Symbol">
e</SPAN>
<SUB CLASS="Subscript">
r</SUB>
<SPAN CLASS="Symbol">
= </SPAN>
3.9, and the permittivity of free space <SPAN CLASS="Symbol">
e</SPAN>
<SUB CLASS="Subscript">
0</SUB>
<SPAN CLASS="Symbol">
= </SPAN>
3.45 <SPAN CLASS="Symbol">
¥</SPAN>
10<SUP CLASS="Superscript">
–11</SUP>
Fm<SUP CLASS="Superscript">
–1</SUP>
.</P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=15092">
</A>
a. Calculate <SPAN CLASS="EquationVariables">
C</SPAN>
for <SPAN CLASS="EquationVariables">
W</SPAN>
= <SPAN CLASS="EquationVariables">
T</SPAN>
= <SPAN CLASS="EquationVariables">
H</SPAN>
= 1 <SPAN CLASS="Symbol">
m</SPAN>
m.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=15093">
</A>
b. Compare this value with the parallel-plate value (assuming no fringing capacitance).</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=15096">
</A>
c. Assume that the interconnect cross-sectional area (i.e., <SPAN CLASS="EquationVariables">
WH</SPAN>
) is kept constant as technology scales, in order to keep the resistance per unit length of the interconnect constant. Assume that the width scales as <SPAN CLASS="EquationVariables">
sW</SPAN>
, the height as <SPAN CLASS="EquationVariables">
sH</SPAN>
, and the thickness as <SPAN CLASS="EquationVariables">
T</SPAN>
/<SPAN CLASS="EquationVariables">
s</SPAN>
, where <SPAN CLASS="EquationVariables">
s</SPAN>
is a scaling factor from one to 0.1. Use a spreadsheet to calculate values for different scaling factors, assuming that for <SPAN CLASS="EquationVariables">
s</SPAN>
<SPAN CLASS="Symbol">
</SPAN>
= 1: <SPAN CLASS="EquationVariables">
W</SPAN>
= <SPAN CLASS="EquationVariables">
T</SPAN>
= <SPAN CLASS="EquationVariables">
H</SPAN>
= 1 <SPAN CLASS="Symbol">
m</SPAN>
m.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=15119">
</A>
d. Plot your results (with <SPAN CLASS="EquationVariables">
C</SPAN>
on the <SPAN CLASS="Emphasis">
y</SPAN>
-axis vs. <SPAN CLASS="EquationVariables">
s</SPAN>
on the <SPAN CLASS="Emphasis">
x</SPAN>
-axis).</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=15139">
</A>
17.10 <A NAME="13391">
</A>
(Coupling capacitance, 30 min.) One of the reasons to follow quasi-ideal scaling for the physical dimensions of the interconnect is to try and reduce the parasitic area capacitance as we scale. (The other reason is to try and keep interconnect resistance constant.) Area capacitance scales as 1/<SPAN CLASS="EquationVariables">
s</SPAN>
by following ideal scaling rules, but scales as 1/<SPAN CLASS="EquationVariables">
s</SPAN>
<SUP CLASS="Superscript">
1.5</SUP>
by using quasi-ideal scaling. Using quasi-ideal scaling means reducing the widths and horizontal spacing of the interconnect by 1/<SPAN CLASS="EquationVariables">
s</SPAN>
and the height of the lines and their vertical separation from other layers by only 1/<SPAN CLASS="EquationVariables">
s</SPAN>
<SUP CLASS="Superscript">
0.5</SUP>
. The effect is rather like turning the interconnects on their sides. As a result we must consider parasitic capacitances other than just the parallel-plate capacitance between two layers. The parasitic capacitance between neighboring interconnects is called <SPAN CLASS="Definition">
coupling capacitance</SPAN>
<A NAME="marker=51420">
</A>
. <SPAN CLASS="Definition">
Fringing capacitance</SPAN>
<A NAME="marker=51423">
</A>
results from the fact that the electric field lines spill out from the edges of a conductor. This means the total parasitic capacitance is greater than if we just considered the capacitance to be formed by two parallel plates.</P>
<P CLASS="Exercise">
<A NAME="pgfId=15151">
</A>
The following equation is an approximate expression for the capacitance per unit length of an isolated conductor of width <SPAN CLASS="EquationVariables">
W</SPAN>
and thickness <SPAN CLASS="EquationVariables">
T</SPAN>
, separated by a distance <SPAN CLASS="EquationVariables">
H</SPAN>
from a conducting plane, and surrounded by a medium of permittivity <SPAN CLASS="Symbol">
e </SPAN>
[<A NAME="Sakurai83">
</A>
Sakurai and Tamaru, 1983]: </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnRight">
<A NAME="pgfId=84758">
</A>
<SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
1</SUB>
/<SPAN CLASS="Symbol">
e</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=84760">
</A>
=</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnLeft">
<A NAME="pgfId=84762">
</A>
<SPAN CLASS="Symbol">
1.15 </SPAN>
(<SPAN CLASS="EquationVariables">
W</SPAN>
/<SPAN CLASS="EquationVariables">
H</SPAN>
) + 2.80 (<SPAN CLASS="EquationVariables">
T</SPAN>
/<SPAN CLASS="EquationVariables">
H</SPAN>
)<SUP CLASS="Superscript">
0.222</SUP>
] .</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnLeft">
<A NAME="pgfId=84764">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=84766">
</A>
(17.13)</P>
</TD>
</TR>
</TABLE>
<P CLASS="Exercise">
<A NAME="pgfId=15310">
</A>
This equation is of the form, </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnRight">
<A NAME="pgfId=84839">
</A>
<SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
1</SUB>
<SPAN CLASS="Symbol">
</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=84841">
</A>
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