ch08.5.htm
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1,316 行
118</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76210">
</A>
3064</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76212">
</A>
270.9</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76214">
</A>
366.5</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76216">
</A>
99,285</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76218">
</A>
0.64</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76220">
</A>
16 <SPAN CLASS="Symbol">
¥</SPAN>
14</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76222">
</A>
1275</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76224">
</A>
142</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76226">
</A>
3090</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76228">
</A>
437.0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76230">
</A>
299.2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76232">
</A>
130,750</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76234">
</A>
0.84</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76236">
</A>
16 <SPAN CLASS="Symbol">
¥</SPAN>
20</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76238">
</A>
1472</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=76240">
</A>
166</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="8">
<P CLASS="TableLeft">
<A NAME="pgfId=76246">
</A>
<SPAN CLASS="Emphasis">
Source:</SPAN>
AT&T Data Book, July 1992, p. 3-75, MN92-024FPGA. 1 mil <SUP CLASS="Superscript">
2</SUP>
= 2.54<SUP CLASS="Superscript">
2</SUP>
<SPAN CLASS="Symbol">
¥</SPAN>
10<SUP CLASS="Superscript">
–6</SUP>
cm<SUP CLASS="Superscript">
2</SUP>
= 6.452 <SPAN CLASS="Symbol">
¥</SPAN>
10<SUP CLASS="Superscript">
–6</SUP>
cm<SUP CLASS="Superscript">
2</SUP>
.</P>
</TD>
</TR>
</TABLE>
<P CLASS="ExerciseHead">
<A NAME="pgfId=13298">
</A>
8.7 (Pad density) <A HREF="CH08.5.htm#38833" CLASS="XRef">
Table 8.12</A>
shows the number of pads on each of the AT&T 3000 (equivalent to the Xilinx XC3000) die. Calculate the pad densities in mil/pad for each part and compare with the figure for the ATT3020 in <A HREF="CH08.5.htm#21969" CLASS="XRef">
Table 8.10</A>
.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=76746">
</A>
8.8 (Xilinx HardWire, 10 min.) Xilinx manufactures nonprogrammable versions of its LCA family of FPGAs. These <A NAME="marker=76767">
</A>
HardWire chips are useful when a customer wishes to convert to high-volume production. The Xilinx 1996 Product overview (p. 16) shows two die photographs: one, an XC3090 (with the four quadrants of 8 <SPAN CLASS="Symbol">
¥</SPAN>
10 CLB matrices visible), which is 32 mm <SPAN CLASS="Symbol">
¥</SPAN>
47 mm; the other shows the HardWire version (24 mm <SPAN CLASS="Symbol">
¥</SPAN>
29 mm). Estimate the die size of the HardWire version from the data in <A HREF="CH08.5.htm#38833" CLASS="XRef">
Table 8.12</A>
and estimate the percentage of a Xilinx LCA that is taken up by SRAM. </P>
<P CLASS="Exercise">
<A NAME="pgfId=76834">
</A>
Answer: 60,500 mils<SUP CLASS="Superscript">
2</SUP>
; 50 %.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=31358">
</A>
8.9 (Xilinx XDE, 10 min.) During his yearly appraisal Dewey explains to you how he improved three Xilinx designs last year and managed to use 100 percent of the CLBs on these LCA chips by means of the XDE manual place-and-route program. As Dewey’s boss, rank Dewey from 1 (bad) to 5 (outstanding) and explain your ranking in a space that has room for no more than 20 words.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=84887">
</A>
8.10 (Clocks, 60 min) (From a discussion on an Internet newsgroup including comments from Peter Alfke of Xilinx) “Xilinx guarantees that the minimum value for any delay parameter is always more than 25 % of the maximum value for that same parameter, as published for the fastest speed grade offered at any time. Many parameters have been reduced significantly over the years, but the clock delay has not. For example, comparing the fastest available XC3020-70 in 1988 with the fastest available XC3020A-6 (1996): </P>
<UL>
<LI CLASS="BulletList">
<A NAME="pgfId=72601">
</A>
logic delay (<SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
ILO</SUB>
) decreased from 9 ns to 4.1 ns </LI>
<LI CLASS="BulletList">
<A NAME="pgfId=72602">
</A>
output-to-pad delay decreased from 10 ns to 5 ns </LI>
<LI CLASS="BulletList">
<A NAME="pgfId=31406">
</A>
internal-clock-to-output pad delay decreased from 13 ns to 7 ns </LI>
</UL>
<P CLASS="Exercise">
<A NAME="pgfId=31407">
</A>
The internal speed has more than doubled, but the worst-case clock distribution delay specification has only changed from 6.0 ns (1988) to 5.7 ns (1996).”</P>
<P CLASS="Exercise">
<A NAME="pgfId=72830">
</A>
Comment on the reasons for these changes and their repercussions.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=31622">
</A>
8.11 (State-machine design) </P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=76434">
</A>
a. (10 min.) Draw the state diagram for the LOG/iC code in <A HREF="CH08.1.htm#29879" CLASS="XRef">
Table 8.2</A>
. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=76435">
</A>
b. (10 min.) Show, using an example input sequence, that the detector works. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=76436">
</A>
c. (10 min.) Show that the state equations and the encoding for the PALASM code in <A HREF="CH08.1.htm#29879" CLASS="XRef">
Table 8.2</A>
correctly describe the sequence detector state machine. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=76437">
</A>
d. (30 min.) Convert this design to a different format of your choice: schematic, low-level design language, or HDL.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=76438">
</A>
e. (30 min.) Simulate and test your design.</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=39004">
</A>
8.12 (FPGA software, 60 min.) Write a minitutorial (less than 2 pages) on using your FPGA design system. An example set of instructions for the Altera MAX PLUS II software on a Unix system are shown below:</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=73291">
</A>
Setup:</P>
<OL>
<LI CLASS="NumberFirst">
<A NAME="pgfId=73292">
</A>
Copy <SPAN CLASS="BodyComputer">
~altera/M+2/maxplus2.ini</SPAN>
into <SPAN CLASS="BodyComputer">
~you/yourDirectory</SPAN>
(call this the working directory).</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=73324">
</A>
Edit <SPAN CLASS="BodyComputer">
maxplus2.ini</SPAN>
and point the <SPAN CLASS="BodyComputer">
DESIGN_NAME</SPAN>
to your design</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=73325">
</A>
Copy <SPAN CLASS="BodyComputer">
~altera/M+2/compass.lmf</SPAN>
and <SPAN CLASS="BodyComputer">
~altera/M+2/compass.edc </SPAN>
into your working directory.</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=73296">
</A>
Copy <SPAN CLASS="BodyComputer">
~altera/M+2/foo.acf</SPAN>
into your working directory and rename it <SPAN CLASS="BodyComputer">
mydesign.acf</SPAN>
if your design name is <SPAN CLASS="BodyComputer">
mydesign.edf</SPAN>
.</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=73297">
</A>
Set the environment as follows:</LI>
</OL>
<P CLASS="ComputerFirst">
<A NAME="pgfId=73298">
</A>
setenv LM_LICENSE_FILE ~altera/maxplus2/adm/license.altera</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=73299">
</A>
set path=($path ~altera/maxplus5.1/bin)</P>
<P CLASS="ExerciseNoIndent">
<A NAME="pgfId=73300">
</A>
and run the programs in batch mode: <SPAN CLASS="BodyComputer">
maxplus2 -c mydesign.edf</SPAN>
. Add to this information on any peculiarities of the system you are using (handling of overwriting of files, filename extensions and when they are created, arguments required to run the programs, and so on).</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=66798">
</A>
8.13 (Help, 20 min.) Print the “help” for the key programs in your FPGA system and form it into a condensed “cheat-sheet.” Most programs echo help instruction when called with a <SPAN CLASS="BodyComputer">
'-help'</SPAN>
or <SPAN CLASS="BodyComputer">
'?'</SPAN>
argument (this ought to be a standard). For example, in the Actel system the key programs are edn2adl, adl2edn, and als (in newer versions adl2edn is now an option to als). <SPAN CLASS="Emphasis">
Hint:</SPAN>
Actel does not use <SPAN CLASS="BodyComputer">
'-help'</SPAN>
argument, but you can get instructions on the syntax for each option individually. <A HREF="CH08.5.htm#12961" CLASS="XRef">
Table 8.13</A>
shows an example for the Xilinx <SPAN CLASS="BodyComputer">
xdelay</SPAN>
program.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableTitle">
<A NAME="pgfId=81171">
</A>
TABLE 8.13 <A NAME="12961">
</A>
Xilinx <SPAN CLASS="BodyComputer">
xdelay</SPAN>
arguments.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Computer">
<A NAME="pgfId=81173">
</A>
usage: xdelay [<options>] [<lcafile> ..]</P>
<P CLASS="Computer">
<A NAME="pgfId=81174">
</A>
where <options> are:</P>
<P CLASS="Computer">
<A NAME="pgfId=81175">
</A>
-help Print this help.</P>
<P CLASS="Computer">
<A NAME="pgfId=81176">
</A>
-timespec Do timespec based delay analysis.</P>
<P CLASS="Computer">
<A NAME="pgfId=81177">
</A>
-s Write short xdelay report.</P>
<P CLASS="Computer">
<A NAME="pgfId=81178">
</A>
-x Write long xdelay report.</P>
<P CLASS="Computer">
<A NAME="pgfId=81179">
</A>
-t <template file> Read <template file>.</P>
<P CLASS="Computer">
<A NAME="pgfId=81180">
</A>
-r Use two letter style block names in output.</P>
<P CLASS="Computer">
<A NAME="pgfId=81181">
</A>
-o <file> Send output to file.</P>
<P CLASS="Computer">
<A NAME="pgfId=81182">
</A>
-w Write design file, after retiming net delays.</P>
<P CLASS="Computer">
<A NAME="pgfId=81183">
</A>
-u <speed> Use the <speed> speed grade.</P>
<P CLASS="Computer">
<A NAME="pgfId=81184">
</A>
-d Don't trace delay paths.</P>
<P CLASS="Computer">
<A NAME="pgfId=81185">
</A>
-convert <input .lca file> <new part type> <output .lca file> </P>
<P CLASS="Computer">
<A NAME="pgfId=81186">
</A>
Convert the input design to a new part type.</P>
<P CLASS="Computer">
<A NAME="pgfId=81187">
</A>
Specify no arguments to run xdelay in interactive mode.</P>
<P CLASS="Computer">
<A NAME="pgfId=81188">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=81189">
</A>
To Select Report Specify Option</P>
<P CLASS="Computer">
<A NAME="pgfId=81190">
</A>
------------------------- ---------------------------</P>
<P CLASS="Computer">
<A NAME="pgfId=81191">
</A>
TimeSpec summary -timespec</P>
<P CLASS="Computer">
<A NAME="pgfId=81192">
</A>
Short path details -s </P>
<P CLASS="Computer">
<A NAME="pgfId=81193">
</A>
Long path details -x </P>
<P CLASS="Computer">
<A NAME="pgfId=81194">
</A>
Analyze summary none of -s, -x or -timespec</P>
<P CLASS="Computer">
<A NAME="pgfId=81195">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=81196">
</A>
A template file can be specified with the -t option to further filter the selected report. Only those template commands relevant to the selected report will be used.</P>
<P CLASS="Computer">
<A NAME="pgfId=81197">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=81198">
</A>
Using -w and -d options together will insert delay information into the design file(s), without tracing any paths.</P>
<P CLASS="Computer">
<A NAME="pgfId=81199">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=81200">
</A>
The -convert option may not be used with any other options.</P>
</TD>
</TR>
</TABLE>
<HR><P>[ <A HREF="CH08.htm">Chapter start</A> ] [ <A HREF="CH08.4.htm">Previous page</A> ] [ <A HREF="CH08.6.htm">Next page</A> ]</P></BODY>
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