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<H1 CLASS="Heading1">
<A NAME="pgfId=4985">
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8.5 <A NAME="10479">
</A>
Problems</H1>
<P CLASS="Exercise">
<A NAME="pgfId=73268">
</A>
* = Difficult, ** = Very difficult, *** = Extremely difficult</P>
<P CLASS="ExerciseHead">
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8.1 (Files, 60 min.) Create a version of <A HREF="CH08.1.htm#37446" CLASS="XRef">
Table 8.1</A>
for your design system.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=84340">
</A>
8.2 (Scripts, 60 min.) Create a version of <A HREF="CH08.3.htm#32987" CLASS="XRef">
Table 8.5</A>
for your design system.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=84861">
</A>
8.3 (Halfgate, 60 min.) </P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=91389">
</A>
a. Using an FPGA of your choice, estimate the preroute delay of a single inverter (including I/O delays).</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=91390">
</A>
b. Complete a halfgate design and explain the postroute delays (make sure you know what conditions are being used—worst-case commercial, for example).</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=78356">
</A>
8.4 (***Xilinx die analysis, 120 min.) The data in <A HREF="CH08.5.htm#21969" CLASS="XRef">
Table 8.10</A>
shows some information derived from a die photo of an ATT3020 (equivalent to a Xilinx 3020) in the AT&T data book. The die photo shows the CLBs clearly enough that we can measure their size. Then, knowing the actual die size, we can calculate the CLB size and other parameters. From your knowledge of the contents of the XC3020 CLB, as well as the programming and interconnect structures, make an estimate (showing all of your approximations and explaining all of your assumptions) of the CLB area and compare this to the value of 277 mils<SUP CLASS="Superscript">
2</SUP>
shown in <A HREF="CH08.5.htm#21969" CLASS="XRef">
Table 8.10</A>
. You will need to calculate the number of logic gates in each CLB including the LUT resources. Estimate how many pass transistors and memory elements are required as well as calculate how many routing resources are assigned to each CLB. <SPAN CLASS="Emphasis">
Hint:</SPAN>
You may need to use the Xilinx software, look at the Xilinx data books, or even the AT&T (Lucent) Orca documentation.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="4">
<P CLASS="TableTitle">
<A NAME="pgfId=66677">
</A>
TABLE 8.10 <A NAME="21969">
</A>
ATT3020 die information (Problem 8.4).</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=66688">
</A>
<SPAN CLASS="TableHeads">
Parameter</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=66690">
</A>
<SPAN CLASS="TableHeads">
Specified in data book</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=66692">
</A>
<SPAN CLASS="TableHeads">
Measured on die photo</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=66694">
</A>
<SPAN CLASS="TableHeads">
Calculated from die photo</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=66696">
</A>
3020 die width</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=66698">
</A>
183.5 mil</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=66700">
</A>
4.1 cm</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=66702">
</A>
—</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=66704">
</A>
3020 die height</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=66706">
</A>
219.3 mil</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=66708">
</A>
4.9 cm</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=66710">
</A>
—</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=66712">
</A>
3000 CLB width</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=66714">
</A>
—</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=66716">
</A>
0.325 cm</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=66718">
</A>
14.55 mil = 370 <SPAN CLASS="Symbol">
m</SPAN>
m</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=66720">
</A>
3000 CLB height</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=66722">
</A>
—</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=92840">
</A>
0.425 cm</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=66726">
</A>
19.02 mil = 483 <SPAN CLASS="Symbol">
m</SPAN>
m</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=66728">
</A>
3000 CLB area</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=66730">
</A>
—</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=66732">
</A>
—</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=66734">
</A>
277 mils <SUP CLASS="Superscript">
2</SUP>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=66736">
</A>
3020 pad pitch</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=66738">
</A>
—</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=66740">
</A>
1.61 mm/pad</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=66742">
</A>
7.21 mil/pad</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="4">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=76282">
</A>
<SPAN CLASS="Emphasis">
Source:</SPAN>
AT&T Data Book, July 1992, p. 3-76, MN92-024FPGA.</P>
</TD>
</TR>
</TABLE>
<P CLASS="ExerciseHead">
<A NAME="pgfId=13468">
</A>
8.5 (***FPGA process, 120 min.) <A HREF="CH08.5.htm#36869" CLASS="XRef">
Table 8.11</A>
describes AT&T’s 0.9 <SPAN CLASS="Symbol">
m</SPAN>
m twin-tub V CMOS process, with 0.75 <SPAN CLASS="Symbol">
m</SPAN>
m minimum design rules and 0.6 <SPAN CLASS="Symbol">
m</SPAN>
m effective channel length and silicided (TiS<SUB CLASS="Subscript">
2</SUB>
) poly, source, and drain. This is the process used by AT&T to second-source the Xilinx XC3000 family of FPGAs. Calculate the parasitic resistance and capacitance parameters for the interconnect. </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="TableTitle">
<A NAME="pgfId=30845">
</A>
TABLE 8.11 <A NAME="36869">
</A>
ATT3000 0.9 <SPAN CLASS="Symbol">
m</SPAN>
m twin-tub V CMOS process (Problem 8.5).</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30849">
</A>
<SPAN CLASS="TableHeads">
Parameter</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30851">
</A>
<SPAN CLASS="TableHeads">
Value</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30853">
</A>
Die thickness, t <SUB CLASS="Subscript">
die</SUB>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=30855">
</A>
21 mil</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30857">
</A>
Wafer diameter, W<SUB CLASS="Subscript">
D</SUB>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=30859">
</A>
5 inch</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30861">
</A>
Wafer thickness, W<SUB CLASS="Subscript">
t</SUB>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=30863">
</A>
25 mil</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30865">
</A>
Minimum feature size, 2<SPAN CLASS="Symbol">
l</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=30867">
</A>
0.75 <SPAN CLASS="Symbol">
m</SPAN>
m</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30869">
</A>
Effective gate length, L <SUB CLASS="Subscript">
eff</SUB>
(<SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel and <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=30871">
</A>
0.6 <SPAN CLASS="Symbol">
m</SPAN>
m </P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30873">
</A>
First-level metal, m1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=30875">
</A>
Ti/AlCuSi</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=30877">
</A>
Second-level metal, m2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=30879">
</A>
AlCuSi</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
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