ch08.3.htm

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 </A>
	<SPAN CLASS="Bold">
or</SPAN>
 or1_5 ( N_10, N_11 );</P>
<P CLASS="Computer">
<A NAME="pgfId=68430">
 </A>
	TRANSPORT transport_6 ( N_11, N_11_A );</P>
<P CLASS="Computer">
<A NAME="pgfId=68431">
 </A>
	<SPAN CLASS="Bold">
defparam</SPAN>
 transport_6.DELAY = 60;</P>
<P CLASS="Computer">
<A NAME="pgfId=68432">
 </A>
	<SPAN CLASS="Bold">
and</SPAN>
 and1_6 ( N_11_A, N_12 );</P>
<P CLASS="Computer">
<A NAME="pgfId=68433">
 </A>
	TRANSPORT transport_7 ( N_12, N_12_A );</P>
<P CLASS="Computer">
<A NAME="pgfId=68434">
 </A>
	<SPAN CLASS="Bold">
defparam</SPAN>
 transport_7.DELAY = 40;</P>
<P CLASS="Computer">
<A NAME="pgfId=68435">
 </A>
	<SPAN CLASS="Bold">
not</SPAN>
 not_7 ( N_12_A, myInput );</P>
<P CLASS="Computer">
<A NAME="pgfId=68436">
 </A>
	TRANSPORT transport_8 ( N_14, N_14_A );</P>
<P CLASS="Computer">
<A NAME="pgfId=68437">
 </A>
	<SPAN CLASS="Bold">
defparam</SPAN>
 transport_8.DELAY = 60;</P>
<P CLASS="Computer">
<A NAME="pgfId=68438">
 </A>
	<SPAN CLASS="Bold">
and</SPAN>
 and1_8 ( N_14_A, gnd );</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=68439">
 </A>
<SPAN CLASS="Bold">
endmodule</SPAN>
 </P>
<P CLASS="Body">
<A NAME="pgfId=68440">
 </A>
The Verilog model for our ASIC, <SPAN CLASS="BodyComputer">
halfgate_p</SPAN>
, is written in terms of other models: <SPAN CLASS="BodyComputer">
and</SPAN>
, <SPAN CLASS="BodyComputer">
xor</SPAN>
, <SPAN CLASS="BodyComputer">
or</SPAN>
, <SPAN CLASS="BodyComputer">
not</SPAN>
, <SPAN CLASS="BodyComputer">
TRI_halfgate_p</SPAN>
, <SPAN CLASS="BodyComputer">
TRANSPORT</SPAN>
. The first four of these are <A NAME="marker=75753">
 </A>
primitive models for basic logic cells and are built into the Verilog simulator. The model for <SPAN CLASS="BodyComputer">
TRI_halfgate_p</SPAN>
 is generated together with the rest of the code. We also need the following model for TRANSPORT, which contains the delay information for the Altera MAX complex PLD. This code is part of a file (<SPAN CLASS="BodyComputer">
alt_max2.vo</SPAN>
) that is generated automatically. </P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=68442">
 </A>
// MAX+plus II Version 5.1 RC6 10/03/94 Wed Jul 17 04:07:10 1996</P>
<P CLASS="Computer">
<A NAME="pgfId=68443">
 </A>
`timescale 100 ps / 100 ps</P>
<P CLASS="Computer">
<A NAME="pgfId=68444">
 </A>
<SPAN CLASS="ComputerKeyword">
module</SPAN>
 TRANSPORT( OUT, IN ); <SPAN CLASS="ComputerKeyword">
input</SPAN>
 IN; <SPAN CLASS="ComputerKeyword">
output</SPAN>
 OUT; <SPAN CLASS="ComputerKeyword">
reg</SPAN>
 OUTR;</P>
<P CLASS="Computer">
<A NAME="pgfId=68445">
 </A>
<SPAN CLASS="ComputerKeyword">
wire</SPAN>
 OUT = OUTR; parameter DELAY = 0;</P>
<P CLASS="Computer">
<A NAME="pgfId=68446">
 </A>
`ifdef ZeroDelaySim </P>
<P CLASS="Computer">
<A NAME="pgfId=68447">
 </A>
	<SPAN CLASS="ComputerKeyword">
always</SPAN>
 @IN OUTR &lt;= IN;</P>
<P CLASS="Computer">
<A NAME="pgfId=68448">
 </A>
`else </P>
<P CLASS="Computer">
<A NAME="pgfId=68449">
 </A>
	<SPAN CLASS="ComputerKeyword">
always</SPAN>
 @IN OUTR &lt;= #DELAY IN;</P>
<P CLASS="Computer">
<A NAME="pgfId=68450">
 </A>
`endif</P>
<P CLASS="Computer">
<A NAME="pgfId=68451">
 </A>
`ifdef Silos</P>
<P CLASS="Computer">
<A NAME="pgfId=68452">
 </A>
	<SPAN CLASS="ComputerKeyword">
initial</SPAN>
 #0 OUTR = IN;</P>
<P CLASS="Computer">
<A NAME="pgfId=68453">
 </A>
`endif</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=68454">
 </A>
<SPAN CLASS="ComputerKeyword">
endmodule</SPAN>
 </P>
<P CLASS="Body">
<A NAME="pgfId=68455">
 </A>
The Altera software can also write the following VHDL postroute netlist:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=68456">
 </A>
-- halfgate_p (EPM7032LC44) MAX+plus II Version 5.1 RC6 10/03/94</P>
<P CLASS="Computer">
<A NAME="pgfId=68457">
 </A>
-- Wed Jul 17 04:07:10 1996</P>
<P CLASS="Computer">
<A NAME="pgfId=68458">
 </A>
LIBRARY IEEE; USE IEEE.std_logic_1164.all;</P>
<P CLASS="Computer">
<A NAME="pgfId=68459">
 </A>
ENTITY n_tri_halfgate_p IS</P>
<P CLASS="Computer">
<A NAME="pgfId=68460">
 </A>
GENERIC (ttri: TIME := 1 ns; ttxz: TIME := 1 ns; ttzx: TIME := 1 ns);</P>
<P CLASS="Computer">
<A NAME="pgfId=68461">
 </A>
PORT (in0 : IN X01Z; oe  : IN X01Z; out0: OUT X01Z);</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=68462">
 </A>
END n_tri_halfgate_p;</P>
<P CLASS="Computer">
<A NAME="pgfId=68463">
 </A>
ARCHITECTURE behavior OF n_tri_halfgate_p IS</P>
<P CLASS="Computer">
<A NAME="pgfId=68464">
 </A>
BEGIN</P>
<P CLASS="Computer">
<A NAME="pgfId=68465">
 </A>
PROCESS (in0, oe) BEGIN</P>
<P CLASS="Computer">
<A NAME="pgfId=68466">
 </A>
	IF oe'EVENT THEN</P>
<P CLASS="Computer">
<A NAME="pgfId=68467">
 </A>
		IF oe = '0' THEN out0 &lt;= TRANSPORT 'Z' AFTER ttxz;</P>
<P CLASS="Computer">
<A NAME="pgfId=68468">
 </A>
		ELSIF oe = '1' THEN out0 &lt;= TRANSPORT in0 AFTER ttzx;</P>
<P CLASS="Computer">
<A NAME="pgfId=68469">
 </A>
		END IF;</P>
<P CLASS="Computer">
<A NAME="pgfId=68470">
 </A>
	ELSIF oe = '1' THEN out0 &lt;= TRANSPORT in0 AFTER ttri;</P>
<P CLASS="Computer">
<A NAME="pgfId=68471">
 </A>
	END IF;</P>
<P CLASS="Computer">
<A NAME="pgfId=68472">
 </A>
END PROCESS;</P>
<P CLASS="Computer">
<A NAME="pgfId=68473">
 </A>
END behavior;</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=68474">
 </A>
LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE work.n_tri_halfgate_p;</P>
<P CLASS="Computer">
<A NAME="pgfId=68475">
 </A>
ENTITY n_halfgate_p IS</P>
<P CLASS="Computer">
<A NAME="pgfId=68476">
 </A>
	PORT ( myInput : IN X01Z; myOutput : OUT X01Z);</P>
<P CLASS="Computer">
<A NAME="pgfId=68477">
 </A>
END n_halfgate_p;</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=68478">
 </A>
ARCHITECTURE EPM7032LC44 OF n_halfgate_p IS</P>
<P CLASS="Computer">
<A NAME="pgfId=68479">
 </A>
SIGNAL gnd : X01Z := '0'; SIGNAL vcc : X01Z := '1';</P>
<P CLASS="Computer">
<A NAME="pgfId=68480">
 </A>
SIGNAL n_8, B1_i1, n_10, n_11, n_12, n_14 : X01Z;</P>
<P CLASS="Computer">
<A NAME="pgfId=68481">
 </A>
COMPONENT n_tri_halfgate_p</P>
<P CLASS="Computer">
<A NAME="pgfId=68482">
 </A>
	GENERIC (ttri, ttxz, ttzx: TIME);</P>
<P CLASS="Computer">
<A NAME="pgfId=68483">
 </A>
	PORT (in0, oe  : IN X01Z; out0 : OUT X01Z);</P>
<P CLASS="Computer">
<A NAME="pgfId=68484">
 </A>
END COMPONENT;</P>
<P CLASS="Computer">
<A NAME="pgfId=68485">
 </A>
BEGIN</P>
<P CLASS="Computer">
<A NAME="pgfId=68486">
 </A>
PROCESS(myInput) BEGIN ASSERT myInput /= 'X' OR Now = 0 ns</P>
<P CLASS="Computer">
<A NAME="pgfId=68487">
 </A>
	REPORT &quot;Unknown value on myInput&quot; SEVERITY Warning;</P>
<P CLASS="Computer">
<A NAME="pgfId=68488">
 </A>
END PROCESS;</P>
<P CLASS="Computer">
<A NAME="pgfId=68489">
 </A>
n_tri_2: n_tri_halfgate_p</P>
<P CLASS="Computer">
<A NAME="pgfId=68490">
 </A>
	GENERIC MAP (ttri =&gt; 4 ns, ttxz =&gt; 6 ns, ttzx =&gt; 6 ns)</P>
<P CLASS="Computer">
<A NAME="pgfId=68491">
 </A>
	PORT MAP (in0 =&gt; n_8, oe =&gt; vcc, out0 =&gt; myOutput);</P>
<P CLASS="Computer">
<A NAME="pgfId=68492">
 </A>
n_delay_3: n_8 &lt;= TRANSPORT B1_i1 AFTER 1 ns;</P>
<P CLASS="Computer">
<A NAME="pgfId=68493">
 </A>
n_xor_4: B1_i1 &lt;= n_10 XOR n_14;</P>
<P CLASS="Computer">
<A NAME="pgfId=68494">
 </A>
n_or_5: n_10 &lt;= n_11;</P>
<P CLASS="Computer">
<A NAME="pgfId=68495">
 </A>
n_and_6: n_11 &lt;= TRANSPORT n_12 AFTER 6 ns;</P>
<P CLASS="Computer">
<A NAME="pgfId=68496">
 </A>
n_not_7: n_12 &lt;= TRANSPORT NOT myInput AFTER 4 ns;</P>
<P CLASS="Computer">
<A NAME="pgfId=68497">
 </A>
n_and_8: n_14 &lt;= TRANSPORT gnd AFTER 6 ns;</P>
<P CLASS="Computer">
<A NAME="pgfId=68498">
 </A>
END EPM7032LC44;</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=68499">
 </A>
LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE work.n_halfgate_p;</P>
<P CLASS="Computer">
<A NAME="pgfId=68500">
 </A>
ENTITY halfgate_p IS </P>
<P CLASS="Computer">
<A NAME="pgfId=68501">
 </A>
	PORT ( myInput : IN std_logic; myOutput : OUT std_logic);</P>
<P CLASS="Computer">
<A NAME="pgfId=68502">
 </A>
END halfgate_p;</P>
<P CLASS="Computer">
<A NAME="pgfId=68503">
 </A>
ARCHITECTURE EPM7032LC44 OF halfgate_p IS</P>
<P CLASS="Computer">
<A NAME="pgfId=68504">
 </A>
COMPONENT n_halfgate_p PORT (myInput : IN X01Z; myOutput : OUT X01Z);</P>
<P CLASS="Computer">
<A NAME="pgfId=68505">
 </A>
END COMPONENT;</P>
<P CLASS="Computer">
<A NAME="pgfId=68506">
 </A>
BEGIN</P>
<P CLASS="Computer">
<A NAME="pgfId=68507">
 </A>
	n_0: n_halfgate_p</P>
<P CLASS="Computer">
<A NAME="pgfId=68508">
 </A>
	PORT MAP ( myInput =&gt; TO_X01Z(myInput), myOutput =&gt; myOutput);</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=68509">
 </A>
END EPM7032LC44;</P>
<P CLASS="Body">
<A NAME="pgfId=68522">
 </A>
The VHDL is a little harder to decipher than the Verilog, so the schematic for the VHDL postroute netlist is shown in <A HREF="CH08.3.htm#41766" CLASS="XRef">
Figure&nbsp;8.2</A>
. This VHDL netlist is identical in function to the Verilog netlist, but the net names and component names are different. Compare <A HREF="CH08.3.htm#41766" CLASS="XRef">
Figure&nbsp;8.2</A>
 with <A HREF="/Humuhumu/from Antibes/Prof.htm#42342" CLASS="XRef">
Figure&nbsp;5.15</A>
(c) in <A HREF="/Humuhumu/from Antibes/Prof.htm#24387" CLASS="XRef">
Section&nbsp;5.4</A>
, &#8220;<A HREF="/Humuhumu/from Antibes/Prof.htm#24387" CLASS="XRef">
Altera MAX</A>
,&#8221; which shows the Altera basic logic cell and <A HREF="/Humuhumu/from Antibes/Prof.htm#23812" CLASS="XRef">
Figure&nbsp;6.23</A>
 in Section&nbsp;6.8, &#8220;Other I/O Cells,&#8221; which describes the Altera I/O cell. The software has fixed the inputs to the various elements in the Altera MAX device to implement a single inverter. </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=74808">
 </A>
<IMG SRC="CH08-8.gif" ALIGN="BASELINE">
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=74811">
 </A>
FIGURE&nbsp;8.2&nbsp;<A NAME="41766">
 </A>
The VHDL version of the postroute Altera MAX 7000 schematic for the halfgate ASIC. Compare this with Figure&nbsp;5.15(c) and Figure&nbsp;6.23.</P>
</TD>
</TR>
</TABLE>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=74763">
 </A>
8.3.4&nbsp;Comparison</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=74764">
 </A>
The halfgate ASIC design illustrates the differences between a nondeterministic coarse-grained FPGA (Xilinx XC4000), a nondeterministic fine-grained FPGA (Actel ACT&nbsp;3), and a deterministic complex PLD (Altera MAX 7000). These differences, summarized as follows, were apparent even in the halfgate design:</P>
<OL>
<LI CLASS="NumberFirst">
<A NAME="pgfId=74767">
 </A>
The Xilinx LCA architecture does not permit an accurate timing analysis until after place and route. This is because of the coarse-grained nondeterministic architecture.</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=74768">
 </A>
The Actel ACT architecture is nondeterministic, but the fine-grained structure allows fairly accurate preroute timing prediction.</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=74769">
 </A>
The Altera MAX complex PLD requires logic to be fitted to the product steering and programmable array logic. The Altera MAX 7000 has an almost deterministic architecture, which allows accurate preroute timing.</LI>
</OL>
</DIV>
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