ch08.3.htm

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; ALSPATCHREV .1</P>
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; NODEID 72705192</P>
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; VAR FAMILY 1400</P>
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; ENDHEADER</P>
<P CLASS="Computer">
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DEF halfgate_io; myInput, myOutput.</P>
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 </A>
USE ADLIB:INBUF; INBUF_2.</P>
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 </A>
USE ADLIB:OUTBUF; OUTBUF_3.</P>
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 </A>
USE ADLIB:INV; u2.</P>
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 </A>
NET DEF_NET_8;  u2:A, INBUF_2:Y.</P>
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 </A>
NET DEF_NET_9;  myInput, INBUF_2:PAD.</P>
<P CLASS="Computer">
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 </A>
NET DEF_NET_11;  OUTBUF_3:D, u2:Y.</P>
<P CLASS="Computer">
<A NAME="pgfId=74602">
 </A>
NET DEF_NET_12;  myOutput, OUTBUF_3:PAD.</P>
<P CLASS="Computer">
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 </A>
END.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
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; HEADER</P>
<P CLASS="Computer">
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; FILEID STF ./halfgate_io.stf c96ef4d8</P>
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&nbsp;</P>
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... lines omitted ... (126 lines total)</P>
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&nbsp;</P>
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DEF halfgate_io.</P>
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USE ; INBUF_2/U0;</P>
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  TPADH:'11:26:37',</P>
<P CLASS="Computer">
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 </A>
  TPADL:'13:30:41',</P>
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  TPADE:'12:29:41',</P>
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  TPADD:'20:48:70',</P>
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  TYH:'8:20:27',</P>
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  TYL:'12:28:39'.</P>
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PIN u2:A;</P>
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  RDEL:'13:31:42',</P>
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  FDEL:'11:26:37'.</P>
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USE ; OUTBUF_3/U0;</P>
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  TPADH:'11:26:37',</P>
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  TPADL:'13:30:41',</P>
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  TPADE:'12:29:41',</P>
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  TPADD:'20:48:70',</P>
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  TYH:'8:20:27',</P>
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  TYL:'12:28:39'.</P>
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PIN OUTBUF_3/U0:D;</P>
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  RDEL:'14:32:45',</P>
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  FDEL:'11:26:37'.</P>
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END.</P>
</TD>
</TR>
</TABLE>
</DIV>
<DIV>
<H2 CLASS="Heading2">
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8.3.3&nbsp;Altera</H2>
<P CLASS="BodyAfterHead">
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Because Altera complex PLDs use a deterministic routing structure, they can be designed more easily using a self-contained software package&#8212;an &#8220;all-in-one&#8221; software package using a single interface. We shall assume that we can generate a netlist that the Altera software can accept using Cadence, Mentor, or Compass software with an Altera design kit (the most convenient format is EDIF).</P>
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<A HREF="CH08.3.htm#22211" CLASS="XRef">
Table&nbsp;8.8</A>
 shows the EDIF preroute netlist in a format that the Altera software can accept. This netlist file describes a single inverter (the line 'cellRef&nbsp;not'). The majority of the EDIF code in <A HREF="CH08.3.htm#22211" CLASS="XRef">
Table&nbsp;8.8</A>
 is a standard template to pass information about how the VDD and VSS nodes are named, which libraries are used, the name of the design, and so on. We shall cover EDIF in Chapter&nbsp;<A HREF="/Humuhumu/from Antibes/Prof.htm#26147" CLASS="XRef">
9</A>
. </P>
<TABLE>
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<P CLASS="TableTitle">
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TABLE&nbsp;8.8&nbsp;<A NAME="22211">
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EDIF netlist in Altera format for the halfgate ASIC.</P>
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</TR>
<TR>
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<P CLASS="Table">
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&nbsp;</P>
<DIV>
<MAP NAME="CH08-7">
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<IMG SRC="CH08-7.gif" USEMAP="#CH08-7">
</DIV>
</TD>
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</TABLE>
<P CLASS="Body">
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<A HREF="CH08.3.htm#35532" CLASS="XRef">
Table&nbsp;8.9</A>
 shows a small part of the reports generated by the Altera software after completion of the place-and-route step. This report tells us how the software has used the basic logic cells, interconnect, and I/O cells to implement our design. With practice it is possible to read the information from reports such as <A HREF="CH08.3.htm#35532" CLASS="XRef">
Table&nbsp;8.9</A>
 directly, but it is a little easier if we also look at the netlist. The EDIF version of postroute netlist for this example is large. Fortunately, the Altera software can also generate a Verilog version of the postroute netlist. Here is the generated Verilog postroute netlist, halfgate_p.vo (not <SPAN CLASS="BodyComputer">
'.v'</SPAN>
), for the halfgate design:</P>
<TABLE>
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TABLE&nbsp;8.9&nbsp;<A NAME="35532">
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Report for the halfgate ASIC fitted to an Altera MAX 7000 complex PLD.</P>
</TD>
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<TR>
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** INPUTS ** </P>
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                                       Shareable</P>
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                                       Expanders     Fan-In    Fan-Out</P>
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 Pin     LC  LAB  Primitive    Code  Total Shared n/a INP  FBK  OUT  FBK  Name</P>
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  43      -   -       INPUT             0      0   0    0    0    0    1  myInput</P>
</TD>
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<TR>
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** OUTPUTS ** </P>
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                                       Shareable</P>
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                                       Expanders     Fan-In    Fan-Out</P>
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 Pin     LC  LAB  Primitive    Code  Total Shared n/a INP  FBK  OUT  FBK  Name</P>
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  41     17    B     OUTPUT     t       0      0   0    1    0    0    0  myOutput</P>
</TD>
</TR>
<TR>
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** LOGIC CELL INTERCONNECTIONS **</P>
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Logic Array Block 'B': </P>
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        +- LC17 myOutput</P>
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        |</P>
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LC      | | A B | Name</P>
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&nbsp;</P>
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Pin</P>
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43   -&gt; * | - * | myInput</P>
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&nbsp;</P>
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* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.</P>
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- = The logic cell or pin is not an input to the logic cell (or LAB).</P>
</TD>
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</TABLE>
<P CLASS="ComputerFirst">
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// halfgate_p (EPM7032LC44) MAX+plus II Version 5.1 RC6 10/03/94 </P>
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// Wed Jul 17 04:07:10 1996</P>
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`timescale 100 ps / 100 ps</P>
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<B CLASS="Keyword">
module</B>
 TRI_halfgate_p( IN, OE, OUT ); <B CLASS="Keyword">
input</B>
 IN; <B CLASS="Keyword">
input</B>
 OE; <B CLASS="Keyword">
output</B>
 OUT;</P>
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bufif1 ( OUT, IN, OE );</P>
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	<B CLASS="Keyword">
specify</B>
</P>
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		<B CLASS="Keyword">
specparam</B>
 TTRI = 40; <B CLASS="Keyword">
specparam</B>
 TTXZ = 60; <B CLASS="Keyword">
specparam</B>
 TTZX  = 60;</P>
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		(IN =&gt; OUT) = (TTRI,TTRI);</P>
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		(OE =&gt; OUT) = (0,0, TTXZ, TTZX, TTXZ, TTZX);</P>
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	<B CLASS="Keyword">
endspecify</B>
</P>
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<B CLASS="Keyword">
endmodule</B>
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<P CLASS="ComputerFirst">
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<B CLASS="Keyword">
module</B>
 halfgate_p (myInput, myOutput);</P>
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	<SPAN CLASS="Bold">
input</SPAN>
 myInput; <SPAN CLASS="Bold">
output</SPAN>
 myOutput; supply0 gnd; supply1 vcc;</P>
<P CLASS="Computer">
<A NAME="pgfId=68423">
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	<SPAN CLASS="Bold">
wire</SPAN>
 B1_i1, myInput, myOutput, N_8, N_10, N_11, N_12, N_14;</P>
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	TRI_halfgate_p tri_2 ( .OUT(myOutput), .IN(N_8), .OE(vcc) );</P>
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	TRANSPORT transport_3 ( N_8, N_8_A );</P>
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	<SPAN CLASS="Bold">
defparam</SPAN>
 transport_3.DELAY = 10;</P>
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	<SPAN CLASS="Bold">
and</SPAN>
 delay_3 ( N_8_A, B1_i1 );</P>
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	<SPAN CLASS="Bold">
xor</SPAN>
 xor2_4 ( B1_i1, N_10, N_14 );</P>
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