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<TITLE> 8.3 The Halfgate ASIC</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
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<H1 CLASS="Heading1">
<A NAME="pgfId=74358">
</A>
8.3 <A NAME="23727">
</A>
The Halfgate ASIC</H1>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=67252">
</A>
This section illustrates FPGA design using a very simple ASIC—a single inverter. The hidden details of the design and construction of this “halfgate FPGA” are quite complicated. Fortunately, most of the inner workings of the design software are normally hidden from the designer. However, when software breaks, as it sometimes does, it is important to know how things work in order to fix the problem. The formats, filenames, and flow will change, but the information needed at each stage and the order in which it is conveyed will stay much the same.</P>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=67257">
</A>
8.3.1 Xilinx</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=75526">
</A>
<A HREF="CH08.3.htm#32987" CLASS="XRef">
Table 8.5</A>
shows an FPGA design flow using Compass and Xilinx software. On the left of <A HREF="CH08.3.htm#32987" CLASS="XRef">
Table 8.5</A>
is a script for the Compass programs—scripts for Cadence, Mentor, and Synopsys software are similar, but not all design software has the capability to be run on autopilot using scripts and a command language. The diagrams in <A HREF="CH08.3.htm#32987" CLASS="XRef">
Table 8.5</A>
illustrate what is happening at each of the design steps. The following numbered comments, corresponding to the labels in <A HREF="CH08.3.htm#32987" CLASS="XRef">
Table 8.5</A>
, highlight the important steps:</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="TableTitle">
<A NAME="pgfId=75536">
</A>
TABLE 8.5 <A NAME="32987">
</A>
Design flow for the Xilinx implementation of the halfgate ASIC.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=75540">
</A>
Script</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=75542">
</A>
Design flow</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Computer">
<A NAME="pgfId=93232">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=93233">
</A>
# halfgate.xilinx.inp</P>
<P CLASS="Computer">
<A NAME="pgfId=93234">
</A>
shell setdef</P>
<P CLASS="Computer">
<A NAME="pgfId=75547">
</A>
path working xc4000d xblox cmosch000x </P>
<P CLASS="Computer">
<A NAME="pgfId=75548">
</A>
quit</P>
<P CLASS="Computer">
<A NAME="pgfId=75549">
</A>
asic</P>
<P CLASS="Computer">
<A NAME="pgfId=75550">
</A>
open [v]halfgate</P>
<P CLASS="Computer">
<A NAME="pgfId=75551">
</A>
synthesize</P>
<P CLASS="Computer">
<A NAME="pgfId=75552">
</A>
save [nls]halfgate_p</P>
<P CLASS="Computer">
<A NAME="pgfId=75553">
</A>
quit</P>
<P CLASS="Computer">
<A NAME="pgfId=75554">
</A>
fpga</P>
<P CLASS="Computer">
<A NAME="pgfId=75555">
</A>
set tag xc4000</P>
<P CLASS="Computer">
<A NAME="pgfId=75556">
</A>
set opt area</P>
<P CLASS="Computer">
<A NAME="pgfId=75557">
</A>
optimize [nls]halfgate_p</P>
<P CLASS="Computer">
<A NAME="pgfId=75558">
</A>
quit</P>
<P CLASS="Computer">
<A NAME="pgfId=75559">
</A>
qtv</P>
<P CLASS="Computer">
<A NAME="pgfId=75560">
</A>
open [nls]halfgate_p</P>
<P CLASS="Computer">
<A NAME="pgfId=75561">
</A>
trace critical</P>
<P CLASS="Computer">
<A NAME="pgfId=75562">
</A>
print trace [txt]halfgate_p</P>
<P CLASS="Computer">
<A NAME="pgfId=75563">
</A>
quit</P>
<P CLASS="Computer">
<A NAME="pgfId=75564">
</A>
shell vuterm</P>
<P CLASS="Computer">
<A NAME="pgfId=75565">
</A>
exec xnfmerge -p 4003PC84 halfgate_p > /dev/null</P>
<P CLASS="Computer">
<A NAME="pgfId=75566">
</A>
exec xnfprep halfgate_p > /dev/null</P>
<P CLASS="Computer">
<A NAME="pgfId=75567">
</A>
exec ppr halfgate_p > /dev/null</P>
<P CLASS="Computer">
<A NAME="pgfId=75568">
</A>
exec makebits -w halfgate_p > /dev/null</P>
<P CLASS="Computer">
<A NAME="pgfId=75569">
</A>
exec lca2xnf -g -v halfgate_p halfgate_b > /dev/null</P>
<P CLASS="Computer">
<A NAME="pgfId=75570">
</A>
quit</P>
<P CLASS="Computer">
<A NAME="pgfId=75571">
</A>
manager notice</P>
<P CLASS="Computer">
<A NAME="pgfId=75572">
</A>
utility netlist</P>
<P CLASS="Computer">
<A NAME="pgfId=75573">
</A>
open [xnf]halfgate_b</P>
<P CLASS="Computer">
<A NAME="pgfId=75574">
</A>
save [nls]halfgate_b</P>
<P CLASS="Computer">
<A NAME="pgfId=75575">
</A>
save [edf]halfgate_b</P>
<P CLASS="Computer">
<A NAME="pgfId=75576">
</A>
quit</P>
<P CLASS="Computer">
<A NAME="pgfId=75577">
</A>
qtv</P>
<P CLASS="Computer">
<A NAME="pgfId=75578">
</A>
open [nls]halfgate_b</P>
<P CLASS="Computer">
<A NAME="pgfId=75579">
</A>
trace critical</P>
<P CLASS="Computer">
<A NAME="pgfId=75580">
</A>
print trace [txt]halfgate_b</P>
<P CLASS="Computer">
<A NAME="pgfId=75581">
</A>
quit</P>
<P CLASS="Computer">
<A NAME="pgfId=75582">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=75583">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=75584">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=75585">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=75600">
</A>
</P>
<DIV>
<IMG SRC="CH08-2.gif">
</DIV>
</TD>
</TR>
</TABLE>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableTitle">
<A NAME="pgfId=75603">
</A>
TABLE 8.6 <A NAME="38255">
</A>
The Xilinx files for the halfgate ASIC.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=75611">
</A>
Verilog file <SPAN CLASS="BodyComputer">
(halfgate.v)</SPAN>
</P>
<DIV>
<IMG SRC="CH08-3.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=75637">
</A>
Preroute XNF file<SPAN CLASS="BodyComputer">
(halfgate_p.xnf) </SPAN>
</P>
<DIV>
<MAP NAME="CH08-4">
</MAP>
<IMG SRC="CH08-4.gif" USEMAP="#CH08-4">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=75669">
</A>
LCA file <SPAN CLASS="BodyComputer">
(halfgate_p.lca) </SPAN>
</P>
<DIV>
<MAP NAME="CH08-5">
</MAP>
<IMG SRC="CH08-5.gif" USEMAP="#CH08-5">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=75692">
</A>
Postroute XNF file<SPAN CLASS="BodyComputer">
(halfgate_b.xnf)</SPAN>
</P>
<DIV>
<MAP NAME="CH08-6">
</MAP>
<IMG SRC="CH08-6.gif" USEMAP="#CH08-6">
</DIV>
</TD>
</TR>
</TABLE>
<OL>
<LI CLASS="NumberFirst">
<A NAME="pgfId=67279">
</A>
The Verilog code, in <SPAN CLASS="BodyComputer">
halfgate.v</SPAN>
, describes a single inverter. </LI>
<LI CLASS="NumberList">
<A NAME="pgfId=67280">
</A>
The script runs the logic synthesizer that converts the Verilog description to an inverter (using elements from the Xilinx XC4000 library) and saves the result in a netlist, <SPAN CLASS="BodyComputer">
halfgate_p.nls</SPAN>
(a Compass internal format).</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=67281">
</A>
The script next runs the logic optimizer for FPGAs. This program also adds the I/O pads. In this case, logic optimization implements the inverter by using an inverting output pad. The software writes out the netlist as <SPAN CLASS="BodyComputer">
halfgate_p.xnf</SPAN>
.</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=67282">
</A>
A timing simulation is run on the netlist <SPAN CLASS="BodyComputer">
halfgate_p.nls</SPAN>
(the Compass format netlist). This netlist uses the default delays—every gate has a delay of 1 ns. </LI>
<LI CLASS="NumberList">
<A NAME="pgfId=77447">
</A>
At this point the script has run all of the Xilinx programs required to complete the place-and-route step. The Xilinx programs have created several files, the most important of which is <SPAN CLASS="BodyComputer">
halfgate_p.lca</SPAN>
, which describes the FPGA layout. This postroute netlist is converted to <SPAN CLASS="BodyComputer">
halfgate_b.nls </SPAN>
(the added suffix <SPAN CLASS="BodyComputer">
'b' </SPAN>
stands for back-annotation). Next a timing simulation is performed on the postroute netlist, which now includes delays, to find the delay from the input (<SPAN CLASS="BodyComputer">
myInput</SPAN>
) to the output (<SPAN CLASS="BodyComputer">
myOutput</SPAN>
). This is the critical—and only—path. The simulation (not shown) reveals that the delay is 2.8 ns (for the input buffer) plus 11.6 ns (for the output buffer), for a total delay of 14.4 ns (this is for a XC4003 in a PC84 package, and default speed grade '4').</LI>
</OL>
<P CLASS="Body">
<A NAME="pgfId=77451">
</A>
<A HREF="CH08.3.htm#38255" CLASS="XRef">
Table 8.6</A>
shows the key Xilinx files that are created. The preroute file, <SPAN CLASS="BodyComputer">
halfgate_p.xnf</SPAN>
, describes the IBUF and OBUF library cells but does not contain any delays. The LCA file, <SPAN CLASS="BodyComputer">
halfgate_p.lca</SPAN>
, contains all the physical design information, including the locations of the pads and I/O cells on the FPGA (<SPAN CLASS="BodyComputer">
PAD61</SPAN>
for <SPAN CLASS="BodyComputer">
myInput</SPAN>
and <SPAN CLASS="BodyComputer">
PAD1</SPAN>
for <SPAN CLASS="BodyComputer">
myOutput</SPAN>
), as well as the details of the programmable connections between these I/O Cells. The postroute file, <SPAN CLASS="BodyComputer">
halfgate_b.xnf</SPAN>
, is similar to the preroute version except that now the delays are included. Xilinx assigns delays to a pin (connector or terminal of a cell). In this case 2.8 ns is assigned to the output of the input buffer, 8.6 ns is assigned to the input of the output buffer, and finally 3.0 ns is assigned to the output of the output buffer.</P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=67652">
</A>
8.3.2 Actel</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=75421">
</A>
The key Actel files for the halfgate design are the netlist file, halfgate_io.adl, and the STF delay file for back-annotation, halfgate_io.stf. Both of these files are shown in <A HREF="CH08.3.htm#12602" CLASS="XRef">
Table 8.7</A>
(the STF file is large and only the last few lines, which contain the delay information, are shown in the table). </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="TableTitle">
<A NAME="pgfId=74576">
</A>
TABLE 8.7 <A NAME="12602">
</A>
The Actel files for the halfgate ASIC.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=74580">
</A>
ADL file</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=74582">
</A>
STF file</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Computer">
<A NAME="pgfId=74584">
</A>
; HEADER</P>
<P CLASS="Computer">
<A NAME="pgfId=74585">
</A>
; FILEID ADL ./halfgate_io.adl 85e8053b</P>
<P CLASS="Computer">
<A NAME="pgfId=74586">
</A>
; CHECKSUM 85e8053b</P>
<P CLASS="Computer">
<A NAME="pgfId=74587">
</A>
; PROGRAM certify</P>
<P CLASS="Computer">
<A NAME="pgfId=74588">
</A>
; VERSION 23/1</P>
<P CLASS="Computer">
<A NAME="pgfId=74589">
</A>
; ALSMAJORREV 2</P>
<P CLASS="Computer">
<A NAME="pgfId=74590">
</A>
; ALSMINORREV 3</P>
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