ch08.6.htm

介绍asci设计的一本书

 </A>
Antares (<SPAN CLASS="URL">
<A HREF="http://www.anteresco.com" CLASS="URL">
http://www.anteresco.com</A>
</SPAN>
) is a spin-off from Mentor Corporation formed from <A NAME="marker=77239">
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<A NAME="marker=77240">
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Exemplar Logic, a company specializing in synthesis software for PLDs and FPGAs, and <A NAME="marker=77241">
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Model Technology, who produce a VHDL and Verilog simulator using a common kernel.</P>
<P CLASS="Body">
<A NAME="pgfId=84730">
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<A NAME="marker=77242">
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Cadence (<SPAN CLASS="URL">
<A HREF="http://www.cadence.com" CLASS="URL">
http://www.cadence.com</A>
</SPAN>
) is one of the largest EDA companies. They offer design kits for PLD and FPGA design with its schematic-entry (Composer) and logic-synthesis (Concept) software. The Cadence Web site has some pictures of ASIC and FPGA design flow in its third-party support area. To find these, search for &#8220;FPGA&#8221; from the main menu.</P>
<P CLASS="Body">
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<A NAME="marker=84553">
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Compass Design Automation (<SPAN CLASS="URL">
<A HREF="http://www.avanticorp.com" CLASS="URL">
http://www.compass-da.com</A>
</SPAN>
) is a spin-off from VLSI Technology that specializes in ASIC design software and cell libraries. As part of its system design software, this vendor includes compilers and libraries for Xilinx, Actel, and Altera FPGAs.</P>
<P CLASS="Body">
<A NAME="pgfId=84790">
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<A NAME="marker=77246">
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Data I/O (<SPAN CLASS="URL">
<A HREF="http://www.data-io.com" CLASS="URL">
http://www.data-io.com</A>
</SPAN>
) makes the <A NAME="marker=77247">
 </A>
FutureNet DASH schematic-entry program primarily for IBM-compatible PCs. Version 5 also has an EDIF&nbsp;2&nbsp;0&nbsp;0 netlist writer, and an optional program <A NAME="marker=77249">
 </A>
PLDlinx to convert designs to ABEL. Data I/O's ABEL is a very widely used PLD design standard. Most FPGA software allows the merging of ABEL files with netlists from schematic-entry programs. Usually you have to translate ABEL to PALASM first and then merge the PALASM file with any netlists that you created from schematics. ABEL is available on SUN workstations, IBM-compatible PC-DOS, and Macintosh platforms. The Macintosh version is available through <A NAME="marker=77251">
 </A>
Capilano Computing, using its <A NAME="marker=77252">
 </A>
DesignWorks program. Data I/O has extended its ABEL language for use with FPGA design. <A NAME="marker=84811">
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ABEL-FPGA is a set of software that can accept hardware descriptions in ABEL-HDL. <A NAME="marker=84812">
 </A>
ABEL-HDL is an extension of the ABEL language which is optimized for programmable logic. One of the features of ABEL-HDL is a set of naming extensions, <A NAME="marker=84813">
 </A>
dot extensions, which allow the designer to specify how certain signals will be mapped into an FPGA.</P>
<P CLASS="Body">
<A NAME="pgfId=84798">
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Data I/O also makes a number of programmers. For example, the <A NAME="marker=84803">
 </A>
Unisite PROM programmer can be used to program Actel, Altera MAX, and Xilinx EPLD devices. </P>
<P CLASS="Body">
<A NAME="pgfId=84806">
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Data I/O has recently launched a separate division called <A NAME="marker=77253">
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Synario Design Automation (<SPAN CLASS="URL">
<A HREF="http://www.synario.com" CLASS="URL">
http://www.synario.com</A>
</SPAN>
) that has taken over ABEL and produces a new series of PLD and FPGA design software under the <A NAME="marker=77254">
 </A>
Synario banner. </P>
<P CLASS="Body">
<A NAME="pgfId=84819">
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<A NAME="marker=84822">
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Exemplar, now part of Antares, writes many of the software modules for logic synthesis used by other companies in their FPGA synthesis software. Exemplar provides a software package that allows you to enter hardware descriptions in ABEL, PALASM, CUPL, or Minc formats. </P>
<P CLASS="Body">
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<A NAME="marker=84838">
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ISDATA produces a system called <A NAME="marker=84828">
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LOG/iC that can be used for FPGA design. LOG/iC produces <A NAME="marker=84830">
 </A>
JEDEC fusemap files, which can be converted and merged with netlists created with other vendors&#8217; software. An evaluation diskette contains LOG/iC software that programs the Lattice GAL16V8. ISDATA also makes a program called <A NAME="marker=84831">
 </A>
STATE/view for design using state diagrams and flow charts and works with LOG/iC and ABEL. <A NAME="marker=84832">
 </A>
HINT is a program that accepts a subset of VHDL and compiles to the LOG/iC language.</P>
<P CLASS="Body">
<A NAME="pgfId=84835">
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<A NAME="marker=77255">
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Logical Devices (<SPAN CLASS="URL">
<A HREF="http://www.logicaldevices.com" CLASS="URL">
http://www.logicaldevices.com</A>
</SPAN>
) acquired <A NAME="marker=77256">
 </A>
CUPL, a widely used programming language for PLDs, from Personal CAD Systems in 1987. Most FPGA vendors allow you to use files in CUPL format indirectly. Usually you translate to the PALASM format first in order to incorporate any logic you design with CUPL. Logical Devices also sells EPROM programming hardware. They manufacture programmers for FPGAs. </P>
<P CLASS="Body">
<A NAME="pgfId=77259">
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<A NAME="marker=77258">
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Mentor Graphics Corporation (<SPAN CLASS="URL">
<A HREF="http://www.mentorg.com" CLASS="URL">
http://www.mentorg.com</A>
</SPAN>
) is a large EDA company. Mentor produces schematic-entry and logic-synthesis software, IDEA Station and FPGA Station, that interface to the major FPGA vendors (see also Antares). </P>
<P CLASS="Body">
<A NAME="pgfId=92884">
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<A NAME="marker=92882">
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Minc&#8217;s <A NAME="marker=92883">
 </A>
PLDesigner software allows the entry of PLD designs using a mixture of truth tables, waveforms, Minc's <A NAME="marker=92885">
 </A>
Design Synthesis Language (<A NAME="marker=92886">
 </A>
DSL), schematic entry, or a netlist (in EDIF format). Another Minc program <A NAME="marker=92887">
 </A>
PGADesigner includes the ability to target FPGAs as well as PLDs. This program is compatible with the OrCAD, P-CAD, and FutureNet DASH schematic-entry  programs. </P>
<P CLASS="Body">
<A NAME="pgfId=92889">
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<A NAME="marker=92888">
 </A>
OrCAD (<SPAN CLASS="URL">
<A HREF="http://www.orcad.com" CLASS="URL">
http://www.orcad.com</A>
</SPAN>
) is a popular low-cost PC schematic-entry  program supported directly by a number of FPGA  vendors. </P>
<P CLASS="Body">
<A NAME="pgfId=77267">
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<A NAME="marker=77265">
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Simucad (<SPAN CLASS="URL">
<A HREF="http://www.simucad.com" CLASS="URL">
http://www.simucad.com</A>
</SPAN>
) produces <A NAME="marker=77266">
 </A>
PC-SILOS, a low-cost logic-simulation program for PCs machines. Xilinx used to bundle Simucad with FutureNet DASH in its least expensive, entry-level design kit.</P>
<P CLASS="Body">
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<A NAME="marker=77268">
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Synopsys (<SPAN CLASS="URL">
<A HREF="http://www.synopsys.com" CLASS="URL">
http://www.synopsys.com</A>
</SPAN>
) sells logic-synthesis software. There are two main products: the <A NAME="marker=77270">
 </A>
Design Compiler for ASIC design and the <A NAME="marker=77271">
 </A>
<A NAME="marker=77272">
 </A>
FPGA Compiler for FPGA design. <A NAME="marker=77273">
 </A>
FPGA Express is a PC-based FPGA logic synthesizer. There is an extensive on-line help system available for Synopsys customers.</P>
<P CLASS="Body">
<A NAME="pgfId=77275">
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<A NAME="marker=77274">
 </A>
Tanner Research (<SPAN CLASS="BodyComputer">
<A HREF="http://www.tanner.com" CLASS="URL">
http://www.tanner.com</A>
</SPAN>
) offers a variety of ASIC design software and a <A NAME="marker=77276">
 </A>
&#8220;burning service&#8221;; you send them the download files to program the FPGAs and Tanner Research programs the parts and ships them to you. Tanner Research also offers an Actel schematic library for its schematic-entry program S-Edit.</P>
<P CLASS="Body">
<A NAME="pgfId=77278">
 </A>
<A NAME="marker=77277">
 </A>
Texas Instruments (TI) and Minc produces mapping software between TI's gate arrays and FPGAs (TI&#8217;s relationship with Actel is somewhere between a second-source and a partner). Mapping software allows designers to design for a TI gate array, for example, but prototype in FPGAs. Alternatively you could take an existing FPGA design and map it into a TI gate array. This type of design flow is popular with vendors such as AT&amp;T (Lucent), TI, and Motorola who would like you to prototype with their FPGAs before transferring any high-volume products to their ASICs.</P>
<P CLASS="Body">
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<A NAME="marker=77279">
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Viewlogic (<SPAN CLASS="URL">
<A HREF="http://www.viewlogic.com" CLASS="URL">
http://www.viewlogic.com</A>
</SPAN>
) produces the <A NAME="marker=77280">
 </A>
Workview and PRODesigner systems that are sets of ASIC design programs available on a variety of platforms. The Workview software consists of a schematic-entry  program <A NAME="marker=77282">
 </A>
Viewdraw; two simulators: <A NAME="marker=77283">
 </A>
Viewsim and <A NAME="marker=77284">
 </A>
Viewfault; a synthesis tool, <A NAME="marker=77285">
 </A>
Viewgen; <A NAME="marker=77286">
 </A>
Viewplace for layout interface; <A NAME="marker=77287">
 </A>
Viewtrace <A NAME="marker=77288">
 </A>
for simulation analysis; and Viewwave for graphical display. There is also a package, <A NAME="marker=77289">
 </A>
Viewbase, that is a set of software routines enabling programmers to access Viewlogic's database in order to create EDIF, VHDL, and <A NAME="marker=77290">
 </A>
CFI (<A NAME="marker=77291">
 </A>
CAD Framework Initiative) interfaces. Most of the FPGA vendors have a means to incorporate Viewlogic&#8217;s schematic netlists using Viewlogic&#8217;s <A NAME="marker=77292">
 </A>
WIR netlist format. Viewlogic provides a number of applications notes (TECHniques) and includes a list of bug fixes, software limitations, and workarounds online.</P>
</DIV>
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