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<H1 CLASS="Heading1">
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8.6 <A NAME="37702">
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Bibliography</H1>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=84590">
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There are few books on FPGA design software. Skahill’s book <A NAME="[Skahill, 1996]">
</A>
[1996] covers PLD and FPGA design with Cypress FPGAs and the Cypress Warp design system. Connor has written two articles in EDN describing a complete FPGA design project <A NAME="[Connor, 1992]">
</A>
[1992]. Most of the information on design software is available from the software companies themselves—increasingly in online form. There is still some material that is only available through the BBS or from a <SPAN CLASS="Definition">
file-transfer protocol</SPAN>
<A NAME="marker=84592">
</A>
<SPAN CLASS="Definition">
(ftp)</SPAN>
<A NAME="marker=92860">
</A>
site. There is also a great deal of valuable material available in data books printed between 1990 and 1995, prior to the explosion of the use of the Internet in the late-1990s. I have included pointers to these sources in the following sections.</P>
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8.6.1 FPGA Vendors</H2>
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Actel (<SPAN CLASS="URL">
<A HREF="http://www.actel.com" CLASS="URL">
http://www.actel.com</A>
</SPAN>
) has a <A NAME="marker=84470">
</A>
Frequently Asked Questions (<A NAME="marker=84471">
</A>
FAQ<A NAME="marker=84472">
</A>
) guide that is an indication of the most common problems with FPGA design: </P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=84474">
</A>
Software versions, installation, and security, and not having enough computer memory</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=84475">
</A>
<A NAME="marker=84536">
</A>
X11, <A NAME="marker=84537">
</A>
Motif, and <A NAME="marker=84538">
</A>
OpenWindows—problems with paths and fonts. Compatibility problems with <A NAME="marker=84539">
</A>
Windows 95 and NT</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=84495">
</A>
Including I/O pads in a design using schematic entry and logic synthesis—problems with the commands and the exact syntax to use</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=84496">
</A>
Using third-party software for schematic entry or logic synthesis and libraries—problems with versions and paths</LI>
<LI CLASS="BulletLast">
<A NAME="pgfId=84478">
</A>
<A NAME="marker=84540">
</A>
EDIF netlist issues</LI>
</UL>
<P CLASS="Body">
<A NAME="pgfId=84485">
</A>
It seems most of these problems never go away—they just keep resurfacing. If you design a halfgate ASIC, an inverter, start-to-finish, as soon as you get a new set of software, this will alert you to most of the problems you are likely to encounter. </P>
<P CLASS="Body">
<A NAME="pgfId=84513">
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The May 1989 Actel data book contains details of the early antifuse experiments. The Actel April 1990 data book has a chip photo of the Actel 1010 on the cover (from which some useful information may be derived). Reliability reports and article reprints are now included in the data books (see, for example, <A NAME="[Actel, 1996]">
</A>
[Actel, 1996]). There is PowerPoint presentation on FPGAs (<SPAN CLASS="BodyComputer">
architec.exe</SPAN>
) and the Actel FPGA architecture at its Web site.</P>
<P CLASS="Body">
<A NAME="pgfId=75972">
</A>
The Xilinx data book (see, for example, <A NAME="[Xilinx, 1996]">
</A>
[Xilinx, 1996]) contains several hundred pages of information on LCA parts. Xilinx produced a separate <SPAN CLASS="BookTitle">
User Guide and Tutorials</SPAN>
book that contains over 600 pages of application notes, guides, and tutorials on designing with FPGAs and Xilinx FPGAs in particular. <A NAME="marker=84541">
</A>
XCELL is the quarterly <SPAN CLASS="BookTitle">
Xilinx Newsletter,</SPAN>
first published in 1988. It is available online and contains useful tips and pointers to new application notes. There is an extensive set of Xilinx Application Notes at <SPAN CLASS="URL">
<A HREF="http://www.xilinx.com/apps" CLASS="URL">
http://www.xilinx.com/apps</A>
</SPAN>
. A 250 -page guide to using the Synopsys software (<SPAN CLASS="BodyComputer">
hdl_dg.pdf</SPAN>
) covers many of the problems users experience in using any logic synthesizer for FPGA design.</P>
<P CLASS="Body">
<A NAME="pgfId=84780">
</A>
Xilinx provides design kits for its EPLD FPGAs for third-party software such as the Viewlogic design entry and simulation programs. The interconnect architecture in the Xilinx EPLD FPGA is deterministic and so postlayout timing results are close to prelayout estimates. </P>
<P CLASS="Body">
<A NAME="pgfId=75973">
</A>
<A NAME="marker=84552">
</A>
AMD, before it sold its stake in Xilinx, published the 1989/1990 Programmable Data Array Book, which was distinct from the Xilinx data book. The AMD data book contains useful information and code for programs to download configuration files to Xilinx FPGAs from a PC that are still useful.</P>
<P CLASS="Body">
<A NAME="pgfId=75975">
</A>
Altera publishes a series of loose-leaf application notes on a variety of topics, some of them are in the data book (see, for example <A NAME="[Altera, 1996]">
</A>
[Altera, 1996]), but some are not. Most of these application notes are available as the AN series of documents at <SPAN CLASS="URL">
<A HREF="http://www.altera.com/html/literature" CLASS="URL">
http://www.altera.com/html/literature</A>
</SPAN>
. This includes guides on using Cadence, Mentor, Viewlogic, and Synopsys software. The 100-page Synopsys guide (<SPAN CLASS="BodyComputer">
as_sig.pdf</SPAN>
) explains many of the limitations of logic synthesizers for FPGA design and includes the complete VHDL source code for a voice-mail machine as an example.</P>
<P CLASS="Body">
<A NAME="pgfId=84769">
</A>
<A NAME="marker=84720">
</A>
Atmel has a series of data sheets and application notes for its PLD logic at <SPAN CLASS="URL">
<A HREF="http://www.atmel.com" CLASS="URL">
http://www.atmel.com</A>
</SPAN>
. Some of the data sheets (for the ATV2500, for example, available as <SPAN CLASS="BodyComputer">
doc156.pdf</SPAN>
) also include examples of the use of CUPL and ABEL. An application note in Atmel’s data book (available as <SPAN CLASS="BodyComputer">
doc168.pdf</SPAN>
) includes the ABEL source code for a <A NAME="marker=84722">
</A>
video frame grabber and a description of the <A NAME="marker=84723">
</A>
NTSC video format. Atmel offers a review of its links to third-party software in a section “PLD Software Tools Overview” in its data book (available online as <SPAN CLASS="BodyComputer">
doc150.pdf</SPAN>
at <SPAN CLASS="URL">
<A HREF="http://www.atmel.com/atmel/products" CLASS="URL">
http://www.atmel.com/atmel/products</A>
</SPAN>
). Atmel uses an IBM-compatible PC-based system based on the Viewlogic software. Schematic entry uses Viewdraw and simulation uses Viewsim. Atmel provides a separate program, a <A NAME="marker=84770">
</A>
fitter, to optimize a schematic for its FPGA architecture. The output from this software generates an optimized schematic. The place-and-route software then works with this new schematic. Atmel provides an interactive editor similar to the Xilinx design editor that allows the designer to perform placement manually. Atmel also supports PLD design software such as <A NAME="marker=84771">
</A>
Synario from Data I/O. </P>
<P CLASS="Body">
<A NAME="pgfId=84756">
</A>
The QuickLogic design kit uses the <A NAME="marker=84754">
</A>
ECS (<A NAME="marker=84755">
</A>
Engineering Capture System) developed by the <A NAME="marker=84757">
</A>
CAD/CAM Group and now part of DATA I/O. Simulation uses <A NAME="marker=84758">
</A>
X-SIM, a product of <A NAME="marker=84759">
</A>
Silicon Automation Systems. </P>
<P CLASS="Body">
<A NAME="pgfId=84763">
</A>
Cypress has a low-cost design system (for QuickLogic and its own series of complex PLDs) called Warp that uses VHDL for design entry.</P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=77222">
</A>
8.6.2 <A NAME="19081">
</A>
Third-Party Software</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=77223">
</A>
There is a bewildering array of software and software companies that make, sell, and develop products for PLD and FPGA design. These are referred to as <SPAN CLASS="Definition">
third-party vendors</SPAN>
<A NAME="marker=77224">
</A>
. In the remainder of this section we shall describe (in alphabetical order) some of the available third-party software. This list changes frequently and for more information you might search the EE sites from the Bibliography in Chapter 1.</P>
<P CLASS="Body">
<A NAME="pgfId=77230">
</A>
<A NAME="marker=77227">
</A>
Accel (<SPAN CLASS="BodyComputer">
<A HREF="http://www.edac.org/EDAC/Companies" CLASS="URL">
http://www.edac.org/EDAC/Companies</A>
</SPAN>
) produces <A NAME="marker=77228">
</A>
Tango and <A NAME="marker=77229">
</A>
P-CAD (which used to belong to <A NAME="marker=77231">
</A>
Personal CAD Systems) that are a low-cost and popular schematic-entry and PCB layout software for PCs. Currently there are no FPGA vendors that support P-CAD or Tango directly. The missing ingredient is a set of libraries with the appropriate schematic symbols for the logic macros and cells used by the FPGA vendor. </P>
<P CLASS="Body">
<A NAME="pgfId=77235">
</A>
<A NAME="marker=77233">
</A>
AMD (<SPAN CLASS="URL">
<A HREF="http://www.amd.com" CLASS="URL">
http://www.amd.com</A>
</SPAN>
) produces the <A NAME="marker=77234">
</A>
Mach series of PLDs and is also the owner of PALASM. All of the FPGA vendors use the PALASM and PALASM2 languages as interchange formats. Using PALASM is an easy way to incorporate a PLD into an FPGA.</P>
<P CLASS="Body">
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</A>
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