ch08.1.htm

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VLD</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71548">
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Information, warning, and error messages</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71550">
 </A>
PIN</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71552">
 </A>
Complete pin assignment for the design</P>
</TD>
</TR>
<TR>
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<P CLASS="TableLeft">
<A NAME="pgfId=71554">
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DFR</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71556">
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Information about routability and I/O assignment quality</P>
</TD>
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<TR>
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<P CLASS="TableLeft">
<A NAME="pgfId=71558">
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LOC</P>
</TD>
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<P CLASS="TableLeft">
<A NAME="pgfId=71560">
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Placement of non-I/O macros, pin swapping, and freeway assignment</P>
</TD>
</TR>
<TR>
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<P CLASS="TableLeft">
<A NAME="pgfId=71562">
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PLI</P>
</TD>
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<P CLASS="TableLeft">
<A NAME="pgfId=71564">
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Feedback from placement step</P>
</TD>
</TR>
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<P CLASS="TableLeft">
<A NAME="pgfId=71566">
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SEG</P>
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<P CLASS="TableLeft">
<A NAME="pgfId=71568">
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Assignment of horizontal routing segments</P>
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<P CLASS="TableLeft">
<A NAME="pgfId=93046">
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STF</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=93048">
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Back-annotation timing</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71570">
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RTI</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71572">
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Feedback from routing step</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71574">
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FUS</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71576">
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Fuse coordinates (column-track, row-track)</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71578">
 </A>
DEL</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71580">
 </A>
Delays for input pins, nets, and I/O modules</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71582">
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AVI</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71584">
 </A>
Fuse programming times and currents for last chip programmed</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=87715">
 </A>
Actel software can also map hardware description files from other programmable logic design software into the Actel FPGA architecture. As an example, <A HREF="CH08.1.htm#29879" CLASS="XRef">
Table&nbsp;8.2</A>
 shows a text description of a state machine using an HDL from a company called LOG/iC. You can then convert the LOG/iC code to the PALASM code shown in <A HREF="CH08.1.htm#29879" CLASS="XRef">
Table&nbsp;8.2</A>
. The Actel software can take the PALASM code and merge it with other PALASM files or netlists. </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="TableTitle">
<A NAME="pgfId=71594">
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TABLE&nbsp;8.2&nbsp;<A NAME="29879">
 </A>
FPGA state-machine language.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=71598">
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LOG/iC state-machine language</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71600">
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	<SPAN CLASS="TableHeads">
PALASM version</SPAN>
 </P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Computer">
<A NAME="pgfId=71602">
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*IDENTIFICATION</P>
<P CLASS="Computer">
<A NAME="pgfId=71603">
 </A>
sequence detector</P>
<P CLASS="Computer">
<A NAME="pgfId=71604">
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LOG/iC code</P>
<P CLASS="Computer">
<A NAME="pgfId=71605">
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*X-NAMES</P>
<P CLASS="Computer">
<A NAME="pgfId=71606">
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X; !input</P>
<P CLASS="Computer">
<A NAME="pgfId=71607">
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*Y-NAMES</P>
<P CLASS="Computer">
<A NAME="pgfId=71608">
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D; !output, D = 1 when three 1's appear on X</P>
<P CLASS="Computer">
<A NAME="pgfId=71609">
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*FLOW-TABLE</P>
<P CLASS="Computer">
<A NAME="pgfId=71610">
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;State, X input, Y output,  next state</P>
<P CLASS="Computer">
<A NAME="pgfId=71611">
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	S1,			X1, 				Y0,					F2;</P>
<P CLASS="Computer">
<A NAME="pgfId=71612">
 </A>
	S1,			X0, 				Y0, 					F1;</P>
<P CLASS="Computer">
<A NAME="pgfId=71613">
 </A>
	S2,			X1,				Y0,					F3;</P>
<P CLASS="Computer">
<A NAME="pgfId=71614">
 </A>
	S2,			X0,				Y0,					F1;</P>
<P CLASS="Computer">
<A NAME="pgfId=71615">
 </A>
	S3,			X1,				Y0,					F4;</P>
<P CLASS="Computer">
<A NAME="pgfId=71616">
 </A>
	S3,			X0,				Y0,					F1;</P>
<P CLASS="Computer">
<A NAME="pgfId=71617">
 </A>
	S4,			X1,				Y1,					F4;</P>
<P CLASS="Computer">
<A NAME="pgfId=71618">
 </A>
	S4,			X0,				Y0,					F1;</P>
<P CLASS="Computer">
<A NAME="pgfId=71619">
 </A>
*STATE-ASSIGNMENT</P>
<P CLASS="Computer">
<A NAME="pgfId=71620">
 </A>
BINARY;</P>
<P CLASS="Computer">
<A NAME="pgfId=71621">
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*RUN-CONTROL</P>
<P CLASS="Computer">
<A NAME="pgfId=71622">
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PROGFORMAT = P-EQUATIONS;</P>
<P CLASS="Computer">
<A NAME="pgfId=71623">
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*END</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71625">
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TITLE sequence detector</P>
<P CLASS="TableLeft">
<A NAME="pgfId=71626">
 </A>
CHIP MEALY USER</P>
<P CLASS="TableLeft">
<A NAME="pgfId=71627">
 </A>
CLK Z QQ2 QQ1 X</P>
<P CLASS="TableLeft">
<A NAME="pgfId=71628">
 </A>
EQUATIONS</P>
<P CLASS="TableLeft">
<A NAME="pgfId=71629">
 </A>
Z = X * QQ2 * QQ1</P>
<P CLASS="TableLeft">
<A NAME="pgfId=71630">
 </A>
QQ2 := X * QQ1 + X * QQ2</P>
<P CLASS="TableLeftEnd">
<A NAME="pgfId=71631">
 </A>
QQ1 := X * QQ2 + X * /QQ1</P>
<P CLASS="TableLeft">
<A NAME="pgfId=71632">
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&nbsp;</P>
</TD>
</TR>
</TABLE>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=5938">
 </A>
8.1.3&nbsp;Altera</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=5939">
 </A>
Altera uses a self-contained design system for its complex PLDs that performs design entry, simulation, and programming of the parts. Altera also provides an input and output interface to EDIF so that designers may use third-party schematic entry or a logic synthesizer. We have seen that the interconnect scheme in the Altera complex PLDs is nearly deterministic, simplifying the physical-design software as well as eliminating the need for back-annotation and a postlayout simulation. As Altera FPGAs become larger and more complex, there are some exceptions to this rule. Some special cases require signals to make more than one pass through the routing structures or travel large distances across the Altera FastTrack interconnect. It is possible to tell if this will be the case only by trying to place and route an Altera device.</P>
</DIV>
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