ch14.d.htm

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<P CLASS="Reference">
<A NAME="pgfId=119535">
 </A>
IEEE 1029.1. 1991. IEEE Standard for Waveform and Vector Exchange (WAVES) (ANSI). 96&nbsp;p. IEEE reference numbers: [1-55937-195-1] [SH15032-NYF]. [<A HREF="CH14.c.htm#[IEEE 1029.1-1991]" CLASS="XRef">
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<P CLASS="Reference">
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 </A>
IEEE 1149.1b. 1994. IEEE Std 1149.1-1990 Access Port and Boundary-Scan Architecture. 176&nbsp;p. The first part of this updated standard includes supplement 1149.1a-1993. IEEE reference numbers: [1-55937-350-4] [SH16626-NYK] The second part of this standard is includes 1149.1b-1994 Supplement to IEEE Std 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture (ANSI) (available separately). 80&nbsp;p. IEEE reference numbers: [1-55937-497-7] [SH94256-NYK]. [<A HREF="CH14.2.htm#[IEEE 1149.1b, 1994a]" CLASS="XRef">
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, <A HREF="CH14.2.htm#[IEEE 1149.1b, 1994b]" CLASS="XRef">
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, <A HREF="CH14.2.htm#[IEEE 1149.1b, 1994c]" CLASS="XRef">
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, <A HREF="CH14.2.htm#[IEEE 1149.1b, 1994d]" CLASS="XRef">
reference location</A>
, <A HREF="CH14.2.htm#[IEEE 1149.1b, 1994e]" CLASS="XRef">
reference location</A>
, <A HREF="CH14.2.htm#[IEEE 1149.1b, 1994f]" CLASS="XRef">
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]</P>
<P CLASS="Reference">
<A NAME="pgfId=119533">
 </A>
Jha, N. K., and S. Kundu. 1990. <SPAN CLASS="BookTitle">
Testing and Reliable Design of CMOS Circuits.</SPAN>
 Boston: Kluwer, 231&nbsp;p. ISBN 0792390563. TK7871.99.M44.J49. [<A HREF="CH14.c.htm#[Jha and Kundu, 1990]" CLASS="XRef">
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]</P>
<P CLASS="Reference">
<A NAME="pgfId=109291">
 </A>
Lavagno, L., and A. Sangiovanni-Vincentelli. 1993.<SPAN CLASS="BookTitle">
 Algorithms for Synthesis and Testing of Asynchronous Circuits.</SPAN>
 Boston: Kluwer, 339&nbsp;p. ISBN 0792393643. TK7888.4.L38. [<A HREF="CH14.c.htm#[Lavagno and Sangiovanni-Vincentelli, 1993]" CLASS="XRef">
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]</P>
<P CLASS="Reference">
<A NAME="pgfId=109165">
 </A>
Lee, M. T.-C. 1997. <SPAN CLASS="BookTitle">
High-Level Test Synthesis of Digital VLSI Circuits.</SPAN>
 Boston: Artech House, ISBN 0890069077. TK7874.75.L44. [<A HREF="CH14.c.htm#[Lee, 1997]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=57761">
 </A>
Lombardi, F., and M. Sami (Ed.). 1987. <SPAN CLASS="BookTitle">
Testing and Diagnosis of VLSI and ULSI.</SPAN>
 Norwell, MA: Kluwer, 533&nbsp;p. ISBN 90-247-3794-X. TK7874.N345. A series of 20 research-level papers presented at a NATO advanced Study Institute. Contents: Trends in Design for Testability; Statistical Testing; Fault Models; Fault Detection and Design for Testability of CMOS Logic Circuits; Parallel Computer Systems Testing and Integration; Analog Fault Diagnosis; Spectral Techniques for Digital Testing; Logic Verification, Testing and Their Relationships to Logic Synthesis; Proving the Next Stage from Simulation; Petri Nets and Their Relation to Design Validation and Testing; Functional Test of ASICs and Boards; Fault Simulation Techniques &#8212; Theory and Practical Examples; Threshold-Value Simulation and Test Generation; Behavioral Testing of Programmable Systems; Testing of Processing Arrays; Old and New Approaches for the Repair of Redundant Memories; Reconfiguration of Orthogonal Arrays by Front Deletion; Device Testing and SEM Testing Tools; Advances in Electron Beam Testing. [<A HREF="CH14.c.htm#[Lombardi and Sami, 1987]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=21137">
 </A>
Maunder, C. M., and R. E. Tulloss (Ed.). 1990. <SPAN CLASS="BookTitle">
The Test Access Port and Boundary-Scan Architecture.</SPAN>
 Washington, DC: IEEE Computer Society Press. ISBN 0-8186-9070-4. TK867.T39. [<A HREF="CH14.2.htm#Maunder and Tulloss, 1990" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=21151">
 </A>
Needham, W. M. 1991. <SPAN CLASS="BookTitle">
Designer's Guide to Testable ASIC Devices.</SPAN>
 New York: Van Nostrand Reinhold, 284&nbsp;p. ISBN 0-442-00221-1. TK7874.N385. Practical review of wafer and package testing. Includes summary of features and test file formats used by logic testers. [<A HREF="CH14.c.htm#[Needham, 1991]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=21144">
 </A>
Parker, K. P. 1992. <SPAN CLASS="BookTitle">
The Boundary-Scan Handbook.</SPAN>
 Norwell, MA: Kluwer, 262&nbsp;p. ISBN 0-7923-9270-1. TK7868.P7 P3. Describes BSDL. [<A HREF="CH14.2.htm#Parker, 1992" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=21126">
 </A>
Rajsuman, R. 1994.<SPAN CLASS="BookTitle">
 Iddq Testing for CMOS VLSI.</SPAN>
 Boston: Artech House, 193&nbsp;p. ISBN 0-89006-726-0. TK7871.99.M44R35. [<A HREF="CH14.3.htm#Rajsuman, 1994" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=79677">
 </A>
Rao, G. K. 1993. <SPAN CLASS="BookTitle">
Multilevel Interconnect Technology.</SPAN>
 New York: McGraw-Hill. ISBN 0-07-051224-8. Covers the design of a multilevel interconnect process, and manufacturing and reliability issues. [<A HREF="CH14.3.htm#Rao, 1993" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=79682">
 </A>
Roth, J. P. 1966. &#8220;Diagnosis of automata failures: A calculus and a method.&#8221; <SPAN CLASS="BookTitle">
IBM Journal of Research and Development,</SPAN>
 Vol. 10, no. 4, pp.&nbsp;278&#8211;291. Describes the D-calculus and the D-algorithm. [<A HREF="CH14.5.htm#Roth, 1966" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=79678">
 </A>
Russell, G., and I. L. Sayers. 1989. <SPAN CLASS="BookTitle">
Advanced Simulation and Test Methodologies for VLSI Design.</SPAN>
 London: Van Nostrand Reinhold (International), 378&nbsp;p. ISBN 0-7476-0001-5. TK7874.R89. Good explanations with a simple example of the D-algorithm. [<A HREF="CH14.c.htm#[Russell and Sayers, 1989]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=20967">
 </A>
Sabnis, A. G. (Ed.). 1990. <SPAN CLASS="BookTitle">
VLSI Reliability.</SPAN>
 San Diego: Academic Press. ISBN 0-12-234122-8. Covers ESD, electromigration, packaging issues, quality assurance, failure analysis, radiation damage. [<A HREF="CH14.3.htm#Sabnis, 1990" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=16103">
 </A>
Scheiber, S.F. 1995. <SPAN CLASS="BookTitle">
Building a Successful Board-Test Strategy.</SPAN>
 Boston: Butterworth&#8211;Heineman, 286&nbsp;p. ISBN 0-7506-9432-7. TK7868.P7S33. Practical description from a management point of view of board-level testing. [<A HREF="CH14.2.htm#Scheiber, 1995" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=80773">
 </A>
Schulz, M. H., E. Trischler, and T. M. Sarfert. 1988. &#8220;SOCRATES: a highly efficient automatic test pattern generation system.&#8221; <SPAN CLASS="BookTitle">
IEEE Transactions on Computer-Aided Design,</SPAN>
 Vol. 7, no. 1, pp.&nbsp;126&#8211;137. [<A HREF="CH14.5.htm#[Schulz,   Trischler, and Sarfert, 1988]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=57744">
 </A>
Turino, J. 1990. <SPAN CLASS="BookTitle">
Design to Test&#8212;A Definitive Guide for Electronic Design, Manufacture and Service.</SPAN>
 2nd ed. New York: Van Nostrand Reinhold, 368&nbsp;p. ISBN 0-442-00170-3. TK7874.T83. A small encyclopedia of testing. Includes a general introduction to testability, and guidelines for: system-level, analog, and general circuit testing; board-level guidelines, boundary scan, built-in test, testability buses, mechanical issues, surface-mount technology, test software, documentation, implementation, ad-hoc test techniques and strategies, testability checklists, and a testability rating system. [<A HREF="CH14.c.htm#[Turino, 1990]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=57715">
 </A>
Tsui, F. F. 1987. <SPAN CLASS="BookTitle">
LSI/VLSI Testability Design.</SPAN>
 New York: McGraw-Hill, 700&nbsp;p. ISBN 0-07-065341-0. TK7874.T78. Extensive review of scan-test techniques. Approximately 100-page bibliography of papers published on test from 1962&#8211;1986. [<A HREF="CH14.c.htm#[Tsui, 1987]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=16424">
 </A>
Williams, T. W. (Ed.). 1986. <SPAN CLASS="BookTitle">
VLSI Testing.</SPAN>
 Amsterdam: Elsevier Science, 275&nbsp;p. ISBN 0-444-87895-5 (part of set 0-444-87890-4). TK7874.V5666. Seven papers on fault modeling, test generation, and fault simulation, testable PLA designs, design for testability, memory testing, semiconductor test equipment, and board level test equipment. [<A HREF="CH14.c.htm#[Williams, 1986]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=21207">
 </A>
Yarmolik, V. N. 1990. <SPAN CLASS="BookTitle">
Fault Diagnosis of Digital Circuits.</SPAN>
 New York: Wiley. Translated from Russian text. Covers D-algorithm, LSSD, random and pseudorandom testing and analysis, and signature analysis. [<A HREF="CH14.c.htm#[Yarmolik, 1990]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=109281">
 </A>
Yarmolik, V. N., and I. V. Kachan. 1993. <SPAN CLASS="BookTitle">
Self-Testing VLSI Design. </SPAN>
New York: Elsevier, 345&nbsp;p. ISBN 0-444-89640-6. TK7874.I16. Extensive reference on pseudorandom testing techniques. Includes description of pseudorandom sequence generators and polynomials. [<A HREF="CH14.c.htm#[Yarmolik and Kachan, 1993]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=21208">
 </A>
Zobrist, G.W. (Ed.). 1993. <SPAN CLASS="BookTitle">
VLSI Fault Modeling and Testing Techniques.</SPAN>
 Norwood, NJ: Ablex, 199&nbsp;p. ISBN 0-89391-781-8. TK7874.V5625. Includes six research-level papers on physical fault modeling, testing of CMOS open faults, testing bridging faults, BIST for PLAs, design for testability, and synthesis methods for testable circuits. [<A HREF="CH14.c.htm#[Zobrist, 1993]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Exercise">
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&nbsp;</P>
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