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14.13 <A NAME="10338">
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References</H1>
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Page numbers in brackets after the reference indicate the location in the chapter body.</P>
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Abramovici, M., M. A. Breuer, and A. D. Friedman. 1990. <SPAN CLASS="BookTitle">
Digital Systems Testing and Testable Design.</SPAN>
New York: W. H. Freeman, 653 p. ISBN 0-7167-8179-4. TK7874.A23. Introduction to testing and BIST. See also Breuer, M. A., and A. D. Friedman, 1976. <SPAN CLASS="BookTitle">
Diagnosis and Reliable Design of Digital Systems.</SPAN>
2nd ed. Potomac, MD: Computer Science Press, ISBN 0-914894-57-9. TK7868.D5B73. [<A HREF="CH14.c.htm#[Abramovici, Breuer, and Friedman, 1990]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=126465">
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Agarwal, V. K., and A. S. F. Fung. 1981. “Multiple fault testing of large circuits by single fault test sets.” <SPAN CLASS="BookTitle">
IEEE Transactions on Computing,</SPAN>
Vol. C-30, no. 11, pp. 855–865. [<A HREF="CH14.3.htm#[Agarwal and Fung, 1981]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=57781">
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Bardell, P. H., W. H. McAnney, and J. Savir. 1987. <SPAN CLASS="BookTitle">
Built-In Test for VLSI: Pseudorandom Techniques.</SPAN>
New York: Wiley, 354 p. ISBN 0-471-62463-2. TK7874.B374. [<A HREF="CH14.c.htm#[Bardell, McAnney, and Savir, 1987]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=15965">
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Bartlett, K., et al. 1988. “Multilevel logic minimization using implicit don’t cares,” <SPAN CLASS="BookTitle">
IEEE Transactions on Computer-Aided Design, </SPAN>
Vol. CAD-7, no. 6, pp. 723–740. [<A HREF="CH14.b.htm#[Bartlett, 1988]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=109378">
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Bhattacharya, D., and J. P. Hayes. 1990. <SPAN CLASS="BookTitle">
Hierarchical Modeling for VLSI Circuit Testing.</SPAN>
Boston: Kluwer, 159 p. ISBN 079239058X. TK7874.B484. Contains a good description of the D and PODEM algorithms. [<A HREF="CH14.c.htm#[Bhattacharya and Hayes, 1990]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
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Bleeker, H., P. v. d. Eijnden, and F. de Jong. 1993. <SPAN CLASS="BookTitle">
Boundary-Scan Test: A Practical Approach. </SPAN>
Boston: Kluwer, 225 p. ISBN 0-7923-9296-5. [<A HREF="CH14.2.htm#Bleeker and d. Jong, 1993" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
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Brayton, R. K., G. D. Hachtel, and A. L. Sangiovanni-Vincentelli. 1990. “Multilevel logic synthesis.” <SPAN CLASS="BookTitle">
Proceedings of the IEEE, </SPAN>
Vol. 78, no. 2, pp. 264–300. [<A HREF="CH14.b.htm#[Brayton, 1990]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=57734">
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Butler, K. M., and M. R. Mercer. 1992. <SPAN CLASS="BookTitle">
Assessing Fault Model and Test Quality.</SPAN>
Norwell, MA: Kluwer, 125 p. ISBN 0-7923-9222-1. TK7874.B85. Introductory level discussion of test terminology, fault models and their limitations. Research-level discussion of the use of BDDs, ATPG, and controllability/observability. [<A HREF="CH14.5.htm#Butler and Mercer, 1992" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=57730">
</A>
Chandra, S., et al. 1993. “CrossCheck: an innovative testability solution.” <SPAN CLASS="Emphasis">
IEEE Design & Test of Computers, </SPAN>
Vol. 10, no. 2, pp. 56–68. Describes a gate-array test architecture used by Sony, for example. [<A HREF="CH14.c.htm#[Chandra, 1993]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=109430">
</A>
Chakradhar, S. T., V. D. Agrawal, and M. L. Bushnell. 1991. <SPAN CLASS="Emphasis">
Neural Models and Algorithms for Digital Testing.</SPAN>
Boston: Kluwer, 184 p. ISBN 0792391659. TK7868.L6.C44. [<A HREF="CH14.c.htm#[Chakradhar, Agrawal, and Bushnell, 1991]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=57821">
</A>
Cheng, K.-T., and V. D. Agrawal. 1989. <SPAN CLASS="BookTitle">
Unified Methods for VLSI Simulation and Test Generation.</SPAN>
Norwell, MA: Kluwer, 148 p. ISBN 0-7923-9025-3. TK7874.C525. 377 references. The first three chapters give a good introduction to fault simulation and test vector generation. [<A HREF="CH14.c.htm#[Cheng and Agrawal, 1989]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=57831">
</A>
Eichelberger, E. B., E. Lindblom, J. A. Waicukauski, and T. W. Williams. 1991. <SPAN CLASS="BookTitle">
Structured Logic Testing.</SPAN>
Englewood Cliffs, NJ: Prentice-Hall, 183 p. ISBN 0-13-8536805. TK7868.L6S78. Includes material printed in 19 articles by the authors from 1987 to 1989. [<A HREF="CH14.c.htm#[Eichelberger, Lindblom, Waicukauski, and Williams, 1991]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
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Feugate Jr., R. J., and S. M. McIntyre. 1988. <SPAN CLASS="BookTitle">
Introduction to VLSI Testing.</SPAN>
Englewood Cliffs, NJ: Prentice-Hall, 226 p. ISBN 0134988663. TK7874 .F48. Chapters on: Automated Testing Overview; IC Fabrication and Device Specifications; Testing Integrated Circuits: Parametric Tests; Functional Tests; Example of a Functional Test Program; Characterization testing; Developing Test Patterns; Special Testing Problems: Memories; Special Testing Problems: Microcontrollers; Design for Testability; LSTL Language Summary; Example of a Production Test program; The D-Algorithm. [<A HREF="CH14.c.htm#[Feugate and McIntyre, 1988]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=80761">
</A>
Fujiwara, H., and T. Shimono. 1983. “On the acceleration of test generation algorithms.”<SPAN CLASS="BookTitle">
IEEE Transactions on Computers,</SPAN>
Vol. C-32, no. 12, pp. 1137–1144. Describes the FAN ATPG algorithm. [<A HREF="CH14.5.htm#Fujiwara and Shimono, 1983" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=57851">
</A>
Fritzemeier, R. R., H. T. Nagle, and C. F. Hawkins. 1989. “Fundamentals of testability—a tutorial.” <SPAN CLASS="BookTitle">
IEEE Transactions on Industrial Electronics,</SPAN>
Vol. 36, no. 2, pp. 117–128. 54 refs. A review of testing, failure mechanisms, fault models, fault simulation, testability analysis, and test-generation methods for CMOS VLSI circuits. [<A HREF="CH14.c.htm#[Fritzemeier, Nagle, and Hawkins, 1989]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=57861">
</A>
Ghosh, A., S. Devadas, and A. R. Newton. 1992. <SPAN CLASS="Emphasis">
Sequential Logic Testing and Verification. </SPAN>
Norwell, MA: Kluwer, 214 p. ISBN 0-7923-91888. TK7868.L6G47. Describes test generation algorithms for state machines at a level intended for CAD researchers. [<A HREF="CH14.c.htm#[Ghosh, Devadas, and Newton, 1992]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=79690">
</A>
Goel, P. 1981. “An implicit enumeration algorithm to generate tests for combinational logic circuits.” <SPAN CLASS="BookTitle">
IEEE Transactions on Computers, </SPAN>
Vol. C-30, no. 3, pp. 215–222. [<A HREF="CH14.5.htm#Goel81" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=81321">
</A>
Goldstein, L. H. 1979. “Controllability/observability analysis of digital circuits.” <SPAN CLASS="BookTitle">
IEEE Transactions on Circuits and Systems,</SPAN>
Vol. CAS-26, no. 9, pp. 685–693. Describes SCOAP measures. [<A HREF="CH14.5.htm#Goldstein, 1979" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=57880">
</A>
Golomb, S. W., et al. 1982. <SPAN CLASS="BookTitle">
Shift Register Sequences.</SPAN>
2nd ed. Laguna Hills, CA: Aegean Park Press, 247 p. ISBN 0-89412-048-4. QA267.5.S4 G6. See also: Golomb, S. W., <SPAN CLASS="BookTitle">
Shift Register Sequences</SPAN>
(with portions co-authored by L. R. Welch, R. M. Goldstein and A. W. Hales). San Francisco: Holden-Day (1967), 224 p. QA267.5.S4 G6. The second edition has a long bibliography. [<A HREF="CH14.7.htm#Golomb et al., 1982" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=109451">
</A>
Gulati, R. K., and C. F. Hawkins. (Ed.). 1993. <SPAN CLASS="BookTitle">
IDDQ Testing of VLSI Circuits.</SPAN>
Boston: Kluwer, 120 p. ISBN 0792393155. TK7874.I3223. [<A HREF="CH14.3.htm#[Gulati and Hawkins, 1993]" CLASS="XRef">
reference location</A>
]</P>
<P CLASS="Reference">
<A NAME="pgfId=109455">
</A>
Hughes, J. L. A., and E. J. McCluskey. 1986. “Multiple stuck-at fault coverage of single stuck-at fault test sets.” In <SPAN CLASS="BookTitle">
Proceedings of the IEEE International Test Conference,</SPAN>
pp. 368–374. [<A HREF="CH14.3.htm#[Hughes, 1986]" CLASS="XRef">
reference location</A>
]</P>
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