ch14.6.htm
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<TITLE> 14.6 Scan Test</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
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<P>[ <A HREF="CH14.htm">Chapter start</A> ] [ <A HREF="CH14.5.htm">Previous page</A> ] [ <A HREF="CH14.7.htm">Next page</A> ]</P><!--#include file="AmazonAsic.html"--><HR></DIV>
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14.6 <A NAME="15991">
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Scan Test</H1>
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Sequential logic poses a very difficult ATPG problem. Consider the example of a 32-bit counter with a final carry. If the designer included a reset, we have to clock the counter 2<SUP CLASS="Superscript">
32</SUP>
(approximately 4 <SPAN CLASS="Symbol">
¥</SPAN>
10<SUP CLASS="Superscript">
9</SUP>
) times to check the carry logic. Using a 1 MHz tester clock this requires 4 <SPAN CLASS="Symbol">
¥</SPAN>
10<SUP CLASS="Superscript">
3</SUP>
seconds, 1 hour, or (at approximately $0.25 per second) $1,000 of tester time. Consider a 16-bit state machine implemented using a one-hot state register with 16 D flip-flops. If the designer did not include a reset we have a very complicated initialization problem. A sequential ATPG algorithm must consider over 2000 states when constructing sequential test vectors. In an <SPAN CLASS="Emphasis">
</SPAN>
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ad hoc approach to testing we could construct special reset circuits or create manual test vectors to deal with these special situations, one at a time, as they arise. Instead we can take a <SPAN CLASS="Definition">
structured test </SPAN>
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</A>
approach (also called <SPAN CLASS="Definition">
design for test</SPAN>
<A NAME="marker=105815">
</A>
, though this term covers a wider field).</P>
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We can automatically generate test vectors for combinational logic, but ATPG is much harder for sequential logic. Therefore the most common sequential structured test approach converts sequential logic to combinational logic. In full-scan design we replace every sequential element with a scan flip-flop. The result is an internal form of boundary scan and, if we wish, we can use the IEEE 1149.1 TAP to access (and the boundary-scan controller to control) an internal-scan chain.</P>
<P CLASS="Body">
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<A HREF="CH14.6.htm#33065" CLASS="XRef">
Table 14.9</A>
shows a VHDL model and schematic symbols for a scan flip-flop. There is an area and performance penalty to pay for scan design. The scan MUX adds the delay of a 2:1 MUX to the setup time of the flip-flop; this will directly subtract from the critical path delay. The 2:1 MUX and any separate driver for the scan output also adds approximately 10 percent to the area of the flip-flop (depending on the features present in the original flip-flop). The scan chain must also be routed, and this complicates physical design and adds to the interconnect area. In ASIC design the benefits of eliminating complex sequential ATPG and the addition of observability and controllability usually outweigh these disadvantages.</P>
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TABLE 14.9 <A NAME="33065">
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Scan flip-flop.</P>
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<TR>
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<P CLASS="ComputerFirstLabel">
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<B CLASS="Keyword">
library</B>
IEEE; <B CLASS="Keyword">
use</B>
IEEE.STD_LOGIC_1164.<B CLASS="Keyword">
all</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=82046">
</A>
<B CLASS="Keyword">
entity</B>
DFFSCAN <B CLASS="Keyword">
is</B>
</P>
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<A NAME="pgfId=82047">
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<B CLASS="Keyword">
generic</B>
(reset_value : STD_LOGIC := '0');</P>
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<B CLASS="Keyword">
port</B>
( Q : <B CLASS="Keyword">
out</B>
STD_LOGIC ; D, CLK, RST : <B CLASS="Keyword">
in</B>
STD_LOGIC; </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=82049">
</A>
SCOUT : <B CLASS="Keyword">
out</B>
STD_LOGIC; SCIN, SCEN : <B CLASS="Keyword">
in</B>
STD_LOGIC );</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=82050">
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<B CLASS="Keyword">
end</B>
DFFSCAN;</P>
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</A>
<B CLASS="Keyword">
architecture</B>
behave <B CLASS="Keyword">
of</B>
DFFSCAN <B CLASS="Keyword">
is</B>
</P>
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<A NAME="pgfId=82052">
</A>
<B CLASS="Keyword">
signal</B>
RST_IN, CLK_IN , SCEN_IN , SCIN_IN, D_IN : STD_LOGIC ;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=82053">
</A>
<B CLASS="Keyword">
begin</B>
</P>
<P CLASS="ComputerLabel">
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</A>
RST_IN <= to_X01(RST); CLK_IN <= to_X01(CLK);</P>
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SCEN_IN <= to_X01(SCEN); SCIN_IN <= to_X01(SCIN); D_IN <= to_X01(D);</P>
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DFSCAN : <B CLASS="Keyword">
process</B>
(CLK_IN, RST_IN) <B CLASS="Keyword">
begin</B>
</P>
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<A NAME="pgfId=82057">
</A>
<B CLASS="Keyword">
if</B>
RST_IN = '0' <B CLASS="Keyword">
then</B>
Q <= reset_value; SCOUT <= reset_value;</P>
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</A>
<B CLASS="Keyword">
elsif</B>
RST_IN = '1' <B CLASS="Keyword">
and</B>
rising_edge (CLK_IN) <B CLASS="Keyword">
then</B>
</P>
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</A>
<B CLASS="Keyword">
if</B>
SCEN_IN = '1' <B CLASS="Keyword">
then</B>
Q <= SCIN_IN; SCOUT <= SCIN_IN; </P>
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<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
if</B>
;</P>
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</A>
<B CLASS="Keyword">
elsif</B>
SCEN_IN = '0' <B CLASS="Keyword">
then</B>
Q <= D_IN; SCOUT <= D_IN;</P>
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</A>
<B CLASS="Keyword">
else</B>
Q <= 'X' ; SCOUT <= 'X';</P>
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</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
if</B>
;</P>
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<A NAME="pgfId=82064">
</A>
<B CLASS="Keyword">
elsif</B>
RST_IN = 'X' <B CLASS="Keyword">
or</B>
CLK_IN = 'X' <B CLASS="Keyword">
or</B>
SCEN_IN = 'X' <B CLASS="Keyword">
then </B>
Q <= 'X'; SCOUT <= 'X';</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=82065">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
if</B>
;</P>
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<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
process</B>
DFSCAN;</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=82067">
</A>
<B CLASS="Keyword">
end</B>
behave;</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
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The highly structured nature of full scan allows test software (usually called a <SPAN CLASS="Definition">
test compiler</SPAN>
<A NAME="marker=82138">
</A>
) to perform automatic <SPAN CLASS="Definition">
scan insertion</SPAN>
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</A>
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. Using scan design we turn the output of each flip-flop into a <SPAN CLASS="Definition">
pseudoprimary input</SPAN>
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</A>
and the input to each flip-flop into a <SPAN CLASS="Definition">
pseudoprimary output</SPAN>
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</A>
. ATPG software can then generate test vectors for the combinational logic between scan flip-flops.</P>
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There are other approaches to scan design. In <A NAME="marker=81940">
</A>
<SPAN CLASS="Definition">
partial scan</SPAN>
we replace a subset of the sequential elements with scan flip-flops. We can choose this subset using heuristic procedures to allow the remaining sequential logic to be tested using sequential ATPG techniques. In <A NAME="marker=81942">
</A>
<SPAN CLASS="Definition">
destructive scan</SPAN>
we remove the values at the outputs of the flip-flops during the scan process (this is the usual form of scan design). In <A NAME="marker=81944">
</A>
<SPAN CLASS="Definition">
nondestructive scan</SPAN>
we keep the flip-flop outputs intact so that we can shift out the scan chain and then resume where we left off. <A NAME="marker=81817">
</A>
<SPAN CLASS="Definition">
Level-sensitive scan design</SPAN>
(<A NAME="marker=81818">
</A>
<SPAN CLASS="Definition">
LSSD</SPAN>
<A NAME="marker=81819">
</A>
) is a form of scan design developed at IBM that uses separate clock phases to drive scan elements. </P>
<P CLASS="Body">
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We shall describe scan design, automated scan insertion, and test-program generation with several examples. First, though, we describe another important structured-test technique.</P>
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