📄 ch14.2.htm
字号:
if</B>
(i = 0) <B CLASS="Keyword">
generate</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49019">
</A>
IR_LSB: IR_cell <B CLASS="Keyword">
port</B>
<B CLASS="Keyword">
map</B>
(shiftIR, Vdd, int_scan(i), </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49020">
</A>
clockIR, updateIR, reset_bar, nTRST, Vdd, data_out(i), scan_out);</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49021">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
generate</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49022">
</A>
SECOND : <B CLASS="Keyword">
if</B>
((i = 1) <B CLASS="Keyword">
and</B>
(data_in'HIGH > 1)) <B CLASS="Keyword">
generate</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49023">
</A>
IR1 : IR_cell <B CLASS="Keyword">
port</B>
<B CLASS="Keyword">
map</B>
(shiftIR, GND, int_scan(i),</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49024">
</A>
clockIR, updateIR, reset_bar, nTRST, Vdd, data_out(i), int_scan(i-1));</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49025">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
generate</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49026">
</A>
MIDDLE : <B CLASS="Keyword">
if</B>
((i < data_in'HIGH) <B CLASS="Keyword">
and</B>
(i > 1)) <B CLASS="Keyword">
generate</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49027">
</A>
IRi : IR_cell <B CLASS="Keyword">
port</B>
<B CLASS="Keyword">
map</B>
(shiftIR, data_in(i), int_scan(i),</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49028">
</A>
clockIR, updateIR, reset_bar, nTRST, Vdd, data_out(i), int_scan(i-1));</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49029">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
generate</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49030">
</A>
LAST : <B CLASS="Keyword">
if</B>
(i = data_in'HIGH) <B CLASS="Keyword">
generate</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49031">
</A>
IR_MSB : IR_cell <B CLASS="Keyword">
port</B>
<B CLASS="Keyword">
map</B>
(shiftIR, data_in(i), scan_in, </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49032">
</A>
clockIR, updateIR, reset_bar, nTRST, Vdd, data_out(i), int_scan(i-1));</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49033">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
generate</B>
; <B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
generate</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49034">
</A>
<B CLASS="Keyword">
end</B>
structure;</P>
<P CLASS="Computer">
<A NAME="pgfId=117337">
</A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=117329">
</A>
FIGURE 14.6 <A NAME="28285">
</A>
An IR (instruction register).</P>
</TD>
</TR>
</TABLE>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=124969">
</A>
14.2.3 Instruction Decoder</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=124975">
</A>
<A HREF="CH14.2.htm#19235" CLASS="XRef">
Table 14.4</A>
shows an <SPAN CLASS="Definition">
instruction decoder</SPAN>
<A NAME="marker=124974">
</A>
. This model is capable of decoding the following minimum set of boundary-scan instructions:</P>
<OL>
<LI CLASS="NumberFirst">
<A NAME="pgfId=49496">
</A>
<SPAN CLASS="BodyComputer">
EXTEST</SPAN>
, external test. Drives a known value onto each output pin to test connections between ASICs.</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=49499">
</A>
<SPAN CLASS="BodyComputer">
SAMPLE/PRELOAD</SPAN>
(often abbreviated to <SPAN CLASS="BodyComputer">
SAMPLE</SPAN>
). Performs two functions: first sampling the present input value from input pad during capture; and then preloading the BSC update register output during update (in preparation for an EXTEST instruction, for example).</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=71680">
</A>
<SPAN CLASS="BodyComputer">
IDCODE</SPAN>
. An optional instruction that allows the <SPAN CLASS="Definition">
device-identification register</SPAN>
<A NAME="marker=71678">
</A>
(<A NAME="marker=71707">
</A>
IDCODE) to be shifted out. The IDCODE TDR is an optional register that allows the tester to query the ASIC for the manufacturer’s name, part number, and other data that is shifted out on TDO. <SPAN CLASS="BodyComputer">
IDCODE</SPAN>
defaults to the <SPAN CLASS="BodyComputer">
BYPASS</SPAN>
instruction if there is no IDCODE TDR. </LI>
<LI CLASS="NumberList">
<A NAME="pgfId=49501">
</A>
<SPAN CLASS="BodyComputer">
BYPASS</SPAN>
. Selects the single-cell bypass register (instead of the BSR) and allows data to be quickly shifted between ASICs.</LI>
</OL>
<P CLASS="Body">
<A NAME="pgfId=49518">
</A>
The IEEE 1149.1 standard predefines additional optional instructions and also defines the implementation of custom instructions that may use additional TDRs. </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableTitle">
<A NAME="pgfId=46156">
</A>
TABLE 14.4 <A NAME="19235">
</A>
An IR (instruction register) decoder.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="ComputerFirstLabel">
<A NAME="pgfId=46163">
</A>
<B CLASS="Keyword">
entity</B>
IR_decoder <B CLASS="Keyword">
is</B>
<B CLASS="Keyword">
generic</B>
(width : INTEGER := 4); <B CLASS="Keyword">
port</B>
(</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=46165">
</A>
shiftDR, clockDR, updateDR : BIT; IR_PO : BIT_VECTOR (width-1 <B CLASS="Keyword">
downto</B>
0) ;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=46205">
</A>
test_mode, selectBR, shiftBR, clockBR, shiftBSR, clockBSR, updateBSR : <B CLASS="Keyword">
out</B>
BIT );</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=46167">
</A>
<B CLASS="Keyword">
end</B>
IR_decoder;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=46168">
</A>
<B CLASS="Keyword">
architecture</B>
behave <B CLASS="Keyword">
of</B>
IR_decoder <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=46237">
</A>
<B CLASS="Keyword">
type</B>
INSTRUCTION <B CLASS="Keyword">
is</B>
(EXTEST, SAMPLE_PRELOAD, IDCODE, BYPASS); </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=50597">
</A>
<B CLASS="Keyword">
signal</B>
I : INSTRUCTION;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=46175">
</A>
<B CLASS="Keyword">
begin</B>
<B CLASS="Keyword">
process</B>
(IR_PO) <B CLASS="Keyword">
begin</B>
<B CLASS="Keyword">
case</B>
BIT_VECTOR'( IR_PO(1), IR_PO(0) ) <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=46272">
</A>
<B CLASS="Keyword">
when</B>
"00" => I <= EXTEST; <B CLASS="Keyword">
when</B>
"01" => I <= SAMPLE_PRELOAD;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=46280">
</A>
<B CLASS="Keyword">
when</B>
"10" => I <= IDCODE; <B CLASS="Keyword">
when</B>
"11" => I <= BYPASS; </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=46248">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
case</B>
; <B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
process</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=46309">
</A>
test_mode <= '1' <B CLASS="Keyword">
when</B>
I = EXTEST <B CLASS="Keyword">
else</B>
'0';</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=46336">
</A>
selectBR <= '1' <B CLASS="Keyword">
when</B>
(I = BYPASS <B CLASS="Keyword">
or</B>
I = IDCODE) <B CLASS="Keyword">
else</B>
'0'; </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=46539">
</A>
shiftBR <= shiftDR;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=46334">
</A>
clockBR <= clockDR <B CLASS="Keyword">
when</B>
(I = BYPASS <B CLASS="Keyword">
or</B>
I = IDCODE) <B CLASS="Keyword">
else</B>
'1'; </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=46540">
</A>
shiftBSR <= shiftDR;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=46359">
</A>
clockBSR <= clockDR <B CLASS="Keyword">
when</B>
(I = EXTEST <B CLASS="Keyword">
or</B>
I = SAMPLE_PRELOAD) <B CLASS="Keyword">
else</B>
'1';</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=46419">
</A>
updateBSR <= updateDR <B CLASS="Keyword">
when</B>
(I = EXTEST <B CLASS="Keyword">
or</B>
I = SAMPLE_PRELOAD) <B CLASS="Keyword">
else</B>
'0';</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=46193">
</A>
<B CLASS="Keyword">
end</B>
behave;</P>
</TD>
</TR>
</TABLE>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=44576">
</A>
14.2.4 TAP Controller</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=44257">
</A>
<A HREF="CH14.2.htm#13574" CLASS="XRef">
Figure 14.7</A>
shows the TAP controller finite-state machine. The 16-state diagram contains some symmetry: states with suffix <SPAN CLASS="BodyComputer">
'_DR'</SPAN>
operate on the data registers and those with suffix <SPAN CLASS="BodyComputer">
'_IR'</SPAN>
apply to the instruction register. All transitions between states are determined by the <SPAN CLASS="BodyComputer">
TMS</SPAN>
(test mode select) signal and occur at the rising edge of <SPAN CLASS="BodyComputer">
TCK</SPAN>
, the boundary-scan clock. An optional active-low reset signal, <SPAN CLASS="BodyComputer">
nTRST</SPAN>
or <SPAN CLASS="BodyComputer">
TRST*</SPAN>
, resets the state machine to the initial state, <SPAN CLASS="BodyComputer">
Reset</SPAN>
. If the dedicated <SPAN CLASS="BodyComputer">
nTRST</SPAN>
is not used, there must be a power-on reset signal (POR)—not an existing system reset signal.</P>
<P CLASS="Body">
<A NAME="pgfId=52016">
</A>
The outputs of the TAP controller are not shown in <A HREF="CH14.2.htm#13574" CLASS="XRef">
Figure 14.7</A>
, but are derived from each TAP controller state. The TAP controller operates rather like a four-button digital watch that cycles through several states (alarm, stopwatch, 12 hr / 24 hr, countdown timer, and so on) as you press the buttons. Only the shaded states in <A HREF="CH14.2.htm#13574" CLASS="XRef">
Figure 14.7</A>
affect the ASIC core logic; the other states are intermediate steps. The pause states let the controller jog in place while the tester reloads its memory with a new set of test vectors, for example.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=124987">
</A>
</P>
<DIV>
<IMG SRC="CH14-7.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="ComputerFirstLabel">
<A NAME="pgfId=42457">
</A>
<B CLASS="Keyword">
use</B>
work.TAP.<B CLASS="Keyword">
all</B>
; <B CLASS="Keyword">
entity</B>
TAP_sm_states <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=42458">
</A>
<B CLASS="Keyword">
port</B>
(TMS, TCK, nTRST : <B CLASS="Keyword">
in</B>
BIT; S : <B CLASS="Keyword">
out</B>
TAP_STATE); <B CLASS="Keyword">
end</B>
TAP_sm_states;</P>
<P CLASS="Computer">
<A NAME="pgfId=117348">
</A>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=42460">
</A>
<B CLASS="Keyword">
architecture</B>
behave <B CLASS="Keyword">
of</B>
TAP_sm_states <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=47697">
</A>
<B CLASS="Keyword">
type</B>
STATE_ARRAY <B CLASS="Keyword">
is</B>
<B CLASS="Keyword">
array</B>
(TAP_STATE, 0 to 1) <B CLASS="Keyword">
of</B>
TAP_STATE;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=42461">
</A>
<B CLASS="Keyword">
constant</B>
T : STATE_ARRAY := ( (Run_Idle, Reset),</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=42462">
</A>
(Run_Idle, Select_DR), (Capture_DR, Select_IR), (Shift_DR, Exit1_DR), </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=42463">
</A>
(Shift_DR, Exit1_DR), (Pause_DR, Update_DR), (Pause_DR, Exit2_DR), </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=42464">
</A>
(Shift_DR, Update_DR), (Run_Idle, Select_DR), (Capture_IR, Reset), </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=42465">
</A>
(Shift_IR, Exit1_IR), (Shift_IR, Exit1_IR), (Pause_IR, Update_IR), </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=42466">
</A>
(Pause_IR, Exit2_IR), (Shift_IR, Update_IR), (Run_idle, Select_DR) );</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=42467">
</A>
<B CLASS="Keyword">
begin</B>
<B CLASS="Keyword">
process</B>
(TCK, nTRST) <B CLASS="Keyword">
variable</B>
S_i: TAP_STATE; <B CLASS="Keyword">
begin</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=47454">
</A>
<B CLASS="Keyword">
if</B>
( nTRST = '0' ) <B CLASS="Keyword">
then</B>
S_i := Reset;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=42469">
</A>
<B CLASS="Keyword">
elsif </B>
( TCK = '1' <B CLASS="Keyword">
and</B>
TCK'EVENT ) <B CLASS="Keyword">
then </B>
-- transition on +VE clock edge</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=42470">
</A>
<B CLASS="Keyword">
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