ch14.2.htm

介绍asci设计的一本书

		<B CLASS="Keyword">
if</B>
 (shiftIR = '0') <B CLASS="Keyword">
then</B>
 q1 &lt;= data_in; <B CLASS="Keyword">
else</B>
 q1 &lt;= scan_in; <B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
if</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49209">
 </A>
	<B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
if</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49210">
 </A>
<B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
process</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49211">
 </A>
UPD:<B CLASS="Keyword">
process</B>
 (updateIR, SR) <B CLASS="Keyword">
begin</B>
 </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49212">
 </A>
	<B CLASS="Keyword">
if</B>
 (SR = '0') <B CLASS="Keyword">
then</B>
 data_out &lt;= reset_value;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49213">
 </A>
	<B CLASS="Keyword">
elsif</B>
 ((updateIR = '1') <B CLASS="Keyword">
and</B>
 updateIR'EVENT) <B CLASS="Keyword">
then</B>
 data_out &lt;= q1;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49214">
 </A>
	<B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
if</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49215">
 </A>
<B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
process</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49216">
 </A>
<B CLASS="Keyword">
end</B>
 behave;</P>
<P CLASS="Computer">
<A NAME="pgfId=117287">
 </A>
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=117270">
 </A>
FIGURE&nbsp;14.4&nbsp;<A NAME="42499">
 </A>
An IR (instruction register) cell.</P>
</TD>
</TR>
</TABLE>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=44492">
 </A>
14.2.2&nbsp;BST Registers</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=44742">
 </A>
<A HREF="CH14.2.htm#39868" CLASS="XRef">
Figure&nbsp;14.5</A>
 shows a <SPAN CLASS="Definition">
boundary-scan register</SPAN>
<A NAME="marker=48963">
 </A>
 (<A NAME="marker=48965">
 </A>
<SPAN CLASS="Definition">
BSR</SPAN>
<A NAME="marker=48964">
 </A>
), which consists of a series connection, or chain, of BSCs. The BSR surrounds the ASIC core logic and is connected to the I/O pad cells. The BSR monitors (and optionally controls) the inputs and outputs of an ASIC. The direction of information flow is shown by an arrow on each of the BSCs in <A HREF="CH14.2.htm#39868" CLASS="XRef">
Figure&nbsp;14.5</A>
. The control signal, <SPAN CLASS="BodyComputer">
mode</SPAN>
, is decoded from the IR. Signal <SPAN CLASS="BodyComputer">
mode</SPAN>
 is drawn as common to all cells for the BSR in <A HREF="CH14.2.htm#39868" CLASS="XRef">
Figure&nbsp;14.5</A>
, but that is not always the case.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=117658">
 </A>
<IMG SRC="CH14-5.gif" ALIGN="BASELINE">
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="ComputerFirstLabel">
<A NAME="pgfId=117660">
 </A>
<B CLASS="Keyword">
entity</B>
 BSR <B CLASS="Keyword">
is</B>
 </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117661">
 </A>
<B CLASS="Keyword">
generic</B>
 (width : INTEGER := 3);</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117662">
 </A>
<B CLASS="Keyword">
port</B>
 (shiftDR, clockDR, updateDR, mode, scan_in : BIT; </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117663">
 </A>
	scan_out : <B CLASS="Keyword">
out</B>
 BIT;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117664">
 </A>
	data_in : BIT_VECTOR(width-1 <B CLASS="Keyword">
downto</B>
 0);</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117665">
 </A>
	data_out : <B CLASS="Keyword">
out</B>
 BIT_VECTOR(width-1 <B CLASS="Keyword">
downto</B>
 0));</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=117692">
 </A>
<B CLASS="Keyword">
end</B>
 BSR;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117666">
 </A>
<B CLASS="Keyword">
architecture</B>
 structure <B CLASS="Keyword">
of</B>
 BSR <B CLASS="Keyword">
is</B>
 </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117667">
 </A>
<B CLASS="Keyword">
component</B>
 DR_cell <B CLASS="Keyword">
port</B>
 (</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117668">
 </A>
	mode, data_in, shiftDR, scan_in, clockDR, updateDR : BIT;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117669">
 </A>
	data_out, scan_out : <B CLASS="Keyword">
out</B>
 BIT);</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117670">
 </A>
<B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
component</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117671">
 </A>
<B CLASS="Keyword">
for</B>
 <B CLASS="Keyword">
all </B>
: DR_cell <B CLASS="Keyword">
use</B>
 <B CLASS="Keyword">
entity</B>
 WORK.DR_cell(behave);</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117672">
 </A>
<B CLASS="Keyword">
signal</B>
 int_scan : BIT_VECTOR (data_in'RANGE);</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117673">
 </A>
<B CLASS="Keyword">
begin</B>
 </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117674">
 </A>
BSR : <B CLASS="Keyword">
for</B>
 i <B CLASS="Keyword">
in</B>
 data_in'LOW <B CLASS="Keyword">
to</B>
 data_in'HIGH <B CLASS="Keyword">
generate</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117675">
 </A>
	RIGHT : <B CLASS="Keyword">
if</B>
 (i = 0) <B CLASS="Keyword">
generate</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117676">
 </A>
	BSR_LSB : DR_cell <B CLASS="Keyword">
port</B>
 <B CLASS="Keyword">
map</B>
 (mode, data_in(i), shiftDR,</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117677">
 </A>
	int_scan(i), clockDR, updateDR, data_out(i), scan_out);</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117678">
 </A>
	<B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
generate</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117679">
 </A>
	MIDDLE : <B CLASS="Keyword">
if</B>
 ((i &gt; 0) <B CLASS="Keyword">
and</B>
 (i &lt; data_in'HIGH)) <B CLASS="Keyword">
generate</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117680">
 </A>
	BSR_i : DR_cell <B CLASS="Keyword">
port</B>
 <B CLASS="Keyword">
map</B>
 (mode, data_in(i), shiftDR, </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117681">
 </A>
	int_scan(i), clockDR, updateDR, data_out(i), int_scan(i-1));</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117682">
 </A>
	<B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
generate</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117683">
 </A>
	LFET : <B CLASS="Keyword">
if</B>
 (i = data_in'HIGH) <B CLASS="Keyword">
generate</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117684">
 </A>
	BSR_MSB : DR_cell <B CLASS="Keyword">
port</B>
 <B CLASS="Keyword">
map</B>
 (mode, data_in(i), shiftDR,</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117685">
 </A>
	scan_in, clockDR, updateDR, data_out(i), int_scan(i-1));</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117686">
 </A>
	<B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
generate</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117687">
 </A>
<B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
generate</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117688">
 </A>
<B CLASS="Keyword">
end</B>
 structure;</P>
<P CLASS="Computer">
<A NAME="pgfId=117693">
 </A>
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=117691">
 </A>
FIGURE&nbsp;14.5&nbsp;<A NAME="39868">
 </A>
A BSR (boundary-scan register). An example of the component data-register (DR) cells (used as boundary-scan cells) is shown in <A HREF="CH14.2.htm#14280" CLASS="XRef">
Figure&nbsp;14.2</A>
.</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=51946">
 </A>
<A HREF="CH14.2.htm#28285" CLASS="XRef">
Figure&nbsp;14.6</A>
 shows an <SPAN CLASS="Definition">
instruction register</SPAN>
<A NAME="marker=48984">
 </A>
 (<SPAN CLASS="Definition">
IR</SPAN>
<A NAME="marker=48985">
 </A>
<A NAME="marker=48986">
 </A>
), which consists of at least two IR cells connected in series. The IEEE 1149.1 standard specifies that the IR cell is reset to <SPAN CLASS="BodyComputer">
'00...01' </SPAN>
(the optional <SPAN CLASS="BodyComputer">
IDCODE</SPAN>
 instruction). If there is no IDCODE TDR, then the <SPAN CLASS="BodyComputer">
IDCODE</SPAN>
 instruction defaults to the <SPAN CLASS="BodyComputer">
BYPASS</SPAN>
 instruction. </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Computer">
<A NAME="pgfId=124981">
 </A>
&nbsp;</P>
<DIV>
<IMG SRC="CH14-6.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="ComputerFirstLabel">
<A NAME="pgfId=49004">
 </A>
<B CLASS="Keyword">
entity</B>
 IR <B CLASS="Keyword">
is</B>
 <B CLASS="Keyword">
generic</B>
 (width : INTEGER := 4); <B CLASS="Keyword">
port</B>
 (</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49005">
 </A>
	shiftIR, clockIR, updateIR, reset_bar, nTRST, scan_in : BIT; scan_out : <B CLASS="Keyword">
out</B>
 BIT;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49006">
 </A>
	data_in : BIT_VECTOR (width-1 <B CLASS="Keyword">
downto</B>
 0) ;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49007">
 </A>
	data_out : <B CLASS="Keyword">
out</B>
 BIT_VECTOR (width-1 <B CLASS="Keyword">
downto</B>
 0) ); </P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=49008">
 </A>
<B CLASS="Keyword">
end</B>
 IR;</P>
<P CLASS="Computer">
<A NAME="pgfId=117338">
 </A>
&nbsp;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49009">
 </A>
<B CLASS="Keyword">
architecture</B>
 structure <B CLASS="Keyword">
of</B>
 IR <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49010">
 </A>
<B CLASS="Keyword">
component</B>
 IR_cell <B CLASS="Keyword">
port</B>
 (shiftIR, data_in, scan_in, clockIR, </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49011">
 </A>
	updateIR, reset_bar, nTRST, reset_value : BIT ; data_out, scan_out : <B CLASS="Keyword">
out</B>
 BIT );</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49012">
 </A>
<B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
component</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49013">
 </A>
<B CLASS="Keyword">
for</B>
 <B CLASS="Keyword">
all </B>
: IR_cell <B CLASS="Keyword">
use</B>
 <B CLASS="Keyword">
entity</B>
 WORK.IR_cell(behave);</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49014">
 </A>
<B CLASS="Keyword">
signal</B>
 int_scan : BIT_VECTOR (data_in'RANGE);</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49015">
 </A>
<B CLASS="Keyword">
signal </B>
Vdd : BIT := '1'; <B CLASS="Keyword">
signal </B>
GND : BIT := '0';</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49016">
 </A>
<B CLASS="Keyword">
begin</B>
 </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49017">
 </A>
IRGEN : <B CLASS="Keyword">
for</B>
 i <B CLASS="Keyword">
in</B>
 data_in'LOW <B CLASS="Keyword">
to</B>
 data_in'HIGH <B CLASS="Keyword">
generate</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49018">
 </A>
FIRST : <B CLASS="Keyword">