ch14.2.htm

介绍asci设计的一本书

 </A>
 or <A NAME="marker=72124">
 </A>
nTRST</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72052">
 </A>
Test-reset input signal</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72054">
 </A>
Optional TAP wire, resets the TAP controller (active-low)</P>
</TD>
</TR>
</TABLE>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=42473">
 </A>
14.2.1&nbsp;BST Cells</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=44490">
 </A>
<A HREF="CH14.2.htm#14280" CLASS="XRef">
Figure&nbsp;14.2</A>
 shows a <SPAN CLASS="Definition">
data-register cell</SPAN>
<A NAME="marker=48750">
 </A>
 (<SPAN CLASS="Definition">
DR cell</SPAN>
) that may be used to implement any of the TDRs. The most common DR cell is a <SPAN CLASS="Definition">
boundary-scan cell</SPAN>
<A NAME="marker=48751">
 </A>
 (<SPAN CLASS="Definition">
BS cell</SPAN>
, or <SPAN CLASS="Definition">
BSC</SPAN>
), or <SPAN CLASS="Definition">
boundary-register cell</SPAN>
<A NAME="marker=48752">
 </A>
 (this last name is not abbreviated to BR cell, since this term is reserved for another type of cell) [<A NAME="[IEEE 1149.1b, 1994b]">
 </A>
IEEE 1149.1b-1994, p. 10-18, Fig. 10-16].</P>
<P CLASS="Body">
<A NAME="pgfId=105204">
 </A>
A BSC contains two sequential elements. The <SPAN CLASS="Definition">
capture flip-flop</SPAN>
<A NAME="marker=105202">
 </A>
 or <SPAN CLASS="Definition">
capture register</SPAN>
<A NAME="marker=105203">
 </A>
 is part of a shift register formed by series connection of BSCs. The <SPAN CLASS="Definition">
update flip-flop</SPAN>
<A NAME="marker=105205">
 </A>
, or <SPAN CLASS="Definition">
update latch</SPAN>
<A NAME="marker=105206">
 </A>
, is normally drawn as an edge-triggered D flip-flop, though it may be a transparent latch. The inputs to a BSC are: <SPAN CLASS="Definition">
scan in</SPAN>
<A NAME="marker=105207">
 </A>
 (<SPAN CLASS="Definition">
serial in</SPAN>
<A NAME="marker=105208">
 </A>
 or <SPAN CLASS="Definition">
SI</SPAN>
<A NAME="marker=105209">
 </A>
<A NAME="marker=105210">
 </A>
); <SPAN CLASS="Definition">
data in</SPAN>
<A NAME="marker=105211">
 </A>
 (<SPAN CLASS="Definition">
parallel in</SPAN>
<A NAME="marker=105212">
 </A>
 or <SPAN CLASS="Definition">
PI</SPAN>
<A NAME="marker=105213">
 </A>
<A NAME="marker=105214">
 </A>
); and a control signal, <SPAN CLASS="Definition">
mode</SPAN>
<A NAME="marker=105215">
 </A>
 (also called <SPAN CLASS="Definition">
test / normal</SPAN>
<A NAME="marker=105216">
 </A>
). The BSC outputs are: <SPAN CLASS="Definition">
scan out</SPAN>
<A NAME="marker=105217">
 </A>
 (<SPAN CLASS="Definition">
serial out</SPAN>
<A NAME="marker=105218">
 </A>
 or <SPAN CLASS="Definition">
SO</SPAN>
<A NAME="marker=105219">
 </A>
<A NAME="marker=105220">
 </A>
); <SPAN CLASS="Definition">
data out</SPAN>
<A NAME="marker=105221">
 </A>
 (<SPAN CLASS="Definition">
parallel out</SPAN>
<A NAME="marker=105222">
 </A>
 or <SPAN CLASS="Definition">
PO</SPAN>
<A NAME="marker=105223">
 </A>
<A NAME="marker=105224">
 </A>
). The BSC in <A HREF="CH14.2.htm#14280" CLASS="XRef">
Figure&nbsp;14.2</A>
 is <SPAN CLASS="Definition">
reversible</SPAN>
<A NAME="marker=105256">
 </A>
 and can be used for both chip inputs and outputs. Thus <SPAN CLASS="BodyComputer">
data_in</SPAN>
 may be connected to a pad and <SPAN CLASS="BodyComputer">
data_out</SPAN>
 to the core logic or vice versa.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=117208">
 </A>
&nbsp;</P>
<DIV>
<IMG SRC="CH14-2.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="ComputerFirstLabel">
<A NAME="pgfId=117210">
 </A>
<B CLASS="Keyword">
entity</B>
 DR_cell <B CLASS="Keyword">
is port</B>
 (mode, data_in, shiftDR, scan_in, clockDR, updateDR: BIT;</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=117211">
 </A>
	data_out, scan_out: <B CLASS="Keyword">
out</B>
 BIT ); <B CLASS="Keyword">
end</B>
 DR_cell;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117212">
 </A>
<B CLASS="Keyword">
architecture</B>
 behave <B CLASS="Keyword">
of</B>
 DR_cell <B CLASS="Keyword">
is signal</B>
 q1, q2 : BIT; <B CLASS="Keyword">
begin</B>
 </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117213">
 </A>
CAP : <B CLASS="Keyword">
process</B>
(clockDR) <B CLASS="Keyword">
begin</B>
 <B CLASS="Keyword">
if</B>
 clockDR = '1' <B CLASS="Keyword">
then</B>
 </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117214">
 </A>
	<B CLASS="Keyword">
if</B>
 shiftDR = '0' <B CLASS="Keyword">
then</B>
 q1 &lt;= data_in; <B CLASS="Keyword">
else</B>
 q1 &lt;= scan_in; <B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
if</B>
; <B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
if</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117215">
 </A>
<B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
process</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117216">
 </A>
UPD : <B CLASS="Keyword">
process</B>
(updateDR) <B CLASS="Keyword">
begin</B>
 <B CLASS="Keyword">
if</B>
 updateDR = '1' <B CLASS="Keyword">
then</B>
 q2 &lt;= q1; <B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
if</B>
; <B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
process</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117217">
 </A>
data_out &lt;= data_in <B CLASS="Keyword">
when</B>
 mode = '0' <B CLASS="Keyword">
else</B>
 q2; scan_out &lt;= q1;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=117218">
 </A>
<B CLASS="Keyword">
end</B>
 behave;</P>
<P CLASS="Computer">
<A NAME="pgfId=117222">
 </A>
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=117221">
 </A>
FIGURE&nbsp;14.2&nbsp;<A NAME="14280">
 </A>
A DR (data register) cell. The most common use of this cell is as a boundary-scan cell (BSC).</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=51701">
 </A>
The IEEE 1149.1 standard shows the sequential logic in a BSC controlled by the <A NAME="marker=105257">
 </A>
gated clocks: <SPAN CLASS="BodyComputer">
clockDR</SPAN>
 (whose positive edge occurs at the positive edge of TCK) and <SPAN CLASS="BodyComputer">
updateDR</SPAN>
 (whose positive edge occurs at the negative edge of TCK). The IEEE 1149.1 schematics illustrate the standard but do not define how circuits should be implemented. The function of the circuit in <A HREF="CH14.2.htm#14280" CLASS="XRef">
Figure&nbsp;14.2</A>
 (and its model) follows the IEEE 1149.1 standard and many other published schematics, but this is not necessarily the best, or even a safe, implementation. For example, as drawn here, signals <SPAN CLASS="BodyComputer">
clockDR</SPAN>
 and <SPAN CLASS="BodyComputer">
updateDR</SPAN>
 are gated clocks&#8212;normally to be avoided if possible. The update sequential element is shown as an edge-triggered D flip-flop but may be implemented using a latch.</P>
<P CLASS="Body">
<A NAME="pgfId=44255">
 </A>
<A HREF="CH14.2.htm#16914" CLASS="XRef">
Figure&nbsp;14.3</A>
 [<A NAME="[IEEE 1149.1b, 1994c]">
 </A>
IEEE 1149.1b-1994, Chapter 9] shows a <SPAN CLASS="Definition">
bypass-register cell</SPAN>
<A NAME="marker=48863">
 </A>
 (<SPAN CLASS="Definition">
BR cell</SPAN>
<A NAME="marker=48864">
 </A>
<A NAME="marker=48865">
 </A>
<A NAME="marker=48866">
 </A>
). The BR inputs and outputs, scan in (serial in, SI) and scan out (serial out, SO), have the same names as the DR cell ports, but DR cells and BR cells are not directly connected.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="ComputerFirstLabel">
<A NAME="pgfId=44382">
 </A>
<B CLASS="Keyword">
entity</B>
 BR_cell <B CLASS="Keyword">
is</B>
 <B CLASS="Keyword">
port</B>
 (</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=44383">
 </A>
&nbsp;clockDR,shiftDR,scan_in : BIT; scan_out : <B CLASS="Keyword">
out</B>
 BIT );</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=44384">
 </A>
<B CLASS="Keyword">
end</B>
 BR_cell;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=44385">
 </A>
<B CLASS="Keyword">
architecture</B>
 behave <B CLASS="Keyword">
of</B>
 BR_cell <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=44386">
 </A>
<B CLASS="Keyword">
signal</B>
 t1 : BIT; <B CLASS="Keyword">
begin</B>
 t1 &lt;= shiftDR <B CLASS="Keyword">
and</B>
 scan_in;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=44389">
 </A>
<B CLASS="Keyword">
process</B>
 (clockDR) <B CLASS="Keyword">
begin</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=44390">
 </A>
<B CLASS="Keyword">
	if</B>
 (clockDR = '1') <B CLASS="Keyword">
then</B>
 scan_out &lt;= t1; <B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
if</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=44391">
 </A>
<B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
process</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=44392">
 </A>
<B CLASS="Keyword">
end</B>
 behave;</P>
<P CLASS="Computer">
<A NAME="pgfId=117260">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=45550">
 </A>
&nbsp;</P>
<DIV>
<IMG SRC="CH14-3.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=117250">
 </A>
FIGURE&nbsp;14.3&nbsp;<A NAME="16914">
 </A>
A BR (bypass register) cell.</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=44436">
 </A>
<A HREF="CH14.2.htm#42499" CLASS="XRef">
Figure&nbsp;14.4</A>
 shows an <SPAN CLASS="Definition">
instruction-register cell</SPAN>
<A NAME="marker=48909">
 </A>
 (<SPAN CLASS="Definition">
IR cell</SPAN>
<A NAME="marker=105258">
 </A>
) [<A NAME="[IEEE 1149.1b, 1994d]">
 </A>
IEEE 1149.1b-1994, Chapter 6]. The IR cell inputs are: <SPAN CLASS="BodyComputer">
scan_in</SPAN>
, <SPAN CLASS="BodyComputer">
data_in</SPAN>
; as well as clock, shift, and update signals (with names and functions similar to those of the corresponding signals in the BSC). The reset signals are <SPAN CLASS="BodyComputer">
nTRST</SPAN>
 and <SPAN CLASS="BodyComputer">
reset_bar</SPAN>
 (active-low signals often use an asterisk, <SPAN CLASS="BodyComputer">
reset*</SPAN>
 for example, but this is not a legal VHDL name). The two LSBs of <SPAN CLASS="BodyComputer">
data_in</SPAN>
 must permanently be set to <SPAN CLASS="BodyComputer">
'01'</SPAN>
 (this helps in checking the integrity of the scan chain during testing). The remaining <SPAN CLASS="BodyComputer">
data_in</SPAN>
 bits are status bits under the control of the designer. The update sequential element (sometimes called the <SPAN CLASS="Definition">
shadow register</SPAN>
<A NAME="marker=52266">
 </A>
) in each IR cell may be set or reset (depending on <SPAN CLASS="BodyComputer">
reset_value</SPAN>
). The IR cell outputs are: <SPAN CLASS="BodyComputer">
data_out</SPAN>
 (the instruction bit passed to the instruction decoder) and <SPAN CLASS="BodyComputer">
scan_out</SPAN>
 (the data passed to the next IR cell in the IR).</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=124966">
 </A>
&nbsp;</P>
<DIV>
<IMG SRC="CH14-4.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="ComputerFirstLabel">
<A NAME="pgfId=49201">
 </A>
<B CLASS="Keyword">
entity</B>
 IR_cell <B CLASS="Keyword">
is port</B>
(</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49202">
 </A>
	shiftIR, data_in, scan_in, clockIR, updateIR, reset_bar, nTRST, reset_value : BIT;</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=49203">
 </A>
	data_out, scan_out : <B CLASS="Keyword">
out</B>
 BIT); <B CLASS="Keyword">
end</B>
 IR_cell;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49204">
 </A>
<B CLASS="Keyword">
architecture</B>
 behave <B CLASS="Keyword">
of</B>
 IR_cell <B CLASS="Keyword">
is</B>
 <B CLASS="Keyword">
signal</B>
 q1, SR : BIT; <B CLASS="Keyword">
begin</B>
 </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49205">
 </A>
scan_out &lt;= q1; SR &lt;= reset_bar <B CLASS="Keyword">
and</B>
 nTRST;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49206">
 </A>
CAP:<B CLASS="Keyword">
process</B>
 (clockIR) <B CLASS="Keyword">
begin</B>
 </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49207">
 </A>
	<B CLASS="Keyword">
if</B>
 (clockIR = '1') <B CLASS="Keyword">
then</B>
 </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=49208">
 </A>