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<H1 CLASS="Heading1">
<A NAME="pgfId=2458">
</A>
14.2 <A NAME="25042">
</A>
Boundary-Scan Test</H1>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=104322">
</A>
It is possible to test ICs in dual-in-line packages (DIPs<A NAME="marker=104321">
</A>
) with 0.1 inch (2.5 mm) lead spacing on low-density boards using a <A NAME="marker=104323">
</A>
<SPAN CLASS="Definition">
bed-of-nails tester</SPAN>
with probes that contact test points underneath the board. Mechanical testing becomes difficult with board trace widths and separations below 0.1 mm or 100 mm, package-pin separations of 0.3 mm or less, packages with 200 or more pins, surface-mount packages on both sides of the board, and multilayer boards [<A NAME="Scheiber, 1995">
</A>
Scheiber, 1995].</P>
<P CLASS="Body">
<A NAME="pgfId=104326">
</A>
In 1985 a group of European manufacturers formed the <A NAME="marker=104325">
</A>
<SPAN CLASS="Definition">
Joint European Test Action Group</SPAN>
(<A NAME="marker=104327">
</A>
<SPAN CLASS="Definition">
JETAG</SPAN>
<A NAME="marker=104328">
</A>
) to study board testing. With the addition of North American companies, JETAG became the <A NAME="marker=104329">
</A>
<SPAN CLASS="Definition">
Joint Test Action Group</SPAN>
(<A NAME="marker=104330">
</A>
<SPAN CLASS="Definition">
JTAG</SPAN>
) in 1986. The JTAG 2.0 test standard formed the basis of the <A NAME="marker=104331">
</A>
<SPAN CLASS="Definition">
IEEE Standard 1149.1</SPAN>
<A NAME="marker=104332">
</A>
<SPAN CLASS="Definition">
Test Port and Boundary-Scan Architecture</SPAN>
[<A NAME="[IEEE 1149.1b, 1994a]">
</A>
IEEE 1149.1b, 1994], approved in February 1990 and also approved as a standard by the American National Standards Institute (ANSI) in August 1990 [<A NAME="Bleeker and d. Jong, 1993">
</A>
Bleeker, v. d. Eijnden, and de Jong, 1993; <A NAME="Maunder and Tulloss, 1990">
</A>
Maunder and Tulloss, 1990; <A NAME="Parker, 1992">
</A>
Parker, 1992]. The IEEE standard is still often referred to as JTAG, although there are important differences between the last JTAG specification (version 2.0) and the IEEE 1149.1 standard. </P>
<P CLASS="Body">
<A NAME="pgfId=71935">
</A>
<SPAN CLASS="Definition">
Boundary-scan test</SPAN>
<A NAME="marker=71631">
</A>
(<A NAME="marker=71635">
</A>
<SPAN CLASS="Definition">
BST</SPAN>
) is a method for testing boards using a four-wire interface (five wires with an optional master reset signal). A good analogy would be the <A NAME="marker=104256">
</A>
RS-232 interface for PCs. The BST standard interface was designed to test boards, but it is also useful to test ASICs. The BST interface provides a standard means of communicating with test circuits on-board an ASIC. We do need to include extra circuits on an ASIC in order to use BST. This is an example of increasing the cost and complexity (as well as potentially reducing the performance) of an ASIC to reduce the cost of testing the ASIC and the system.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=104344">
</A>
<IMG SRC="CH14-1.gif" ALIGN="BASELINE">
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=104347">
</A>
FIGURE 14.1 <A NAME="30146">
</A>
IEEE 1149.1 boundary scan. (a) Boundary scan is intended to check for shorts or opens between ICs mounted on a board. (b) Shorts and opens may also occur inside the IC package. (c) The boundary-scan architecture is a long chain of shift registers allowing data to be sent over all the connections between the ICs on a board.</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=2533">
</A>
<A HREF="CH14.2.htm#30146" CLASS="XRef">
Figure 14.1</A>
(a) illustrates failures that may occur on a PCB due to shorts or opens in the copper traces on the board. Less frequently, failures in the ASIC package may also arise from shorts and opens in the wire bonds between the die and the package frame (<A HREF="CH14.2.htm#30146" CLASS="XRef">
Figure 14.1</A>
b). Failures in an ASIC package that occur during ASIC fabrication are caught by the ASIC production test, but stress during automated handling and board assembly may cause package failures. <A HREF="CH14.2.htm#30146" CLASS="XRef">
Figure 14.1</A>
(c) shows how a group of ASICs are linked together in boundary-scan testing. To detect the failures shown in <A HREF="CH14.2.htm#30146" CLASS="XRef">
Figure 14.1</A>
(a) or (b) manufacturers use boundary scan to test every connection between ASICs on a board. During boundary scan, test data is loaded into each ASIC and then driven onto the board traces. Each ASIC monitors its inputs, captures the data received, and then shifts the captured data out. Any defects in the board or ASIC connections will show up as a discrepancy between expected and actual measured continuity data.</P>
<P CLASS="Body">
<A NAME="pgfId=71771">
</A>
In order to include BST on an ASIC, we add a special logic cell to each ASIC I/O pad. These cells are joined together to form a chain and create a boundary-scan shift register that extends around each ASIC. The input to a boundary-scan shift register is the <SPAN CLASS="Definition">
test-data input</SPAN>
<A NAME="marker=71884">
</A>
(<A NAME="marker=71885">
</A>
<SPAN CLASS="Definition">
TDI</SPAN>
). The output of a boundary-scan shift register is the <A NAME="marker=71887">
</A>
<SPAN CLASS="Definition">
test-data output</SPAN>
(<A NAME="marker=71888">
</A>
<SPAN CLASS="Definition">
TDO</SPAN>
). These boundary-scan shift registers are then linked in a serial fashion with the boundary-scan shift registers on other ASICs to form one long boundary-scan shift register. The boundary-scan shift register in each ASIC is one of several <A NAME="marker=2553">
</A>
<SPAN CLASS="Definition">
test-data registers</SPAN>
(<SPAN CLASS="Definition">
TDR</SPAN>
<A NAME="marker=104273">
</A>
) that may be included in each ASIC. All the TDRs in an ASIC are connected directly between the TDI and TDO ports. A special register that decodes instructions provides a way to select a particular TDR and control operation of the boundary-scan test process. </P>
<P CLASS="Body">
<A NAME="pgfId=2563">
</A>
Controlling all of the operations involved in selecting registers, loading data, performing a test, and shifting out results are the <SPAN CLASS="Definition">
test clock</SPAN>
<A NAME="marker=2567">
</A>
(<A NAME="marker=2570">
</A>
<SPAN CLASS="Definition">
TCK</SPAN>
) and <SPAN CLASS="Definition">
test-mode select</SPAN>
<A NAME="marker=2572">
</A>
(<A NAME="marker=2574">
</A>
<SPAN CLASS="Definition">
TMS</SPAN>
). The boundary-scan standard specifies a four-wire test interface using the four signals: TDI, TDO, TCK, and TMS. These four dedicated signals, the <A NAME="marker=95439">
</A>
<SPAN CLASS="Definition">
test-access port</SPAN>
(<A NAME="marker=95441">
</A>
<SPAN CLASS="Definition">
TAP</SPAN>
<A NAME="marker=95442">
</A>
<A NAME="marker=95443">
</A>
), are connected to the TAP controller inside each ASIC. The TAP controller is a state machine clocked on the rising edge of TCK, and with state transitions controlled by the TMS signal. The <A NAME="marker=71743">
</A>
<SPAN CLASS="Definition">
test-reset input signal</SPAN>
(<A NAME="marker=71744">
</A>
<SPAN CLASS="Definition">
TRST*</SPAN>
, <A NAME="marker=71745">
</A>
<SPAN CLASS="Definition">
nTRST</SPAN>
, or <SPAN CLASS="Definition">
TRST</SPAN>
<A NAME="marker=95433">
</A>
—always an active-low signal) is an optional (fifth) dedicated interface pin to reset the TAP controller.</P>
<P CLASS="Body">
<A NAME="pgfId=2583">
</A>
Normally the boundary-scan shift-register cells at each ASIC I/O pad are transparent, allowing signals to pass between the I/O pad and the core logic. When an ASIC is put into boundary-scan test mode, we first tell the TAP controller which TDR to select. The TAP controller then tells each boundary-scan shift register in the appropriate TDR either to capture input data, to shift data to the neighboring cell, or to output data.</P>
<P CLASS="Body">
<A NAME="pgfId=71938">
</A>
There are many acronyms in the IEEE 1149.1 standard (referred to as “<SPAN CLASS="Definition">
dot one</SPAN>
<A NAME="marker=72064">
</A>
”); <A HREF="CH14.2.htm#27543" CLASS="XRef">
Table 14.3</A>
provides a list of the most common terms.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="3">
<P CLASS="TableTitle">
<A NAME="pgfId=71947">
</A>
TABLE 14.3 <A NAME="27543">
</A>
<A NAME="42367">
</A>
Boundary-scan terminology.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71953">
</A>
<SPAN CLASS="TableHeads">
Acronym</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71955">
</A>
<SPAN CLASS="TableHeads">
Meaning</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=71957">
</A>
<SPAN CLASS="TableHeads">
Explanation</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71960">
</A>
BR<A NAME="marker=71959">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71962">
</A>
Bypass register</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71964">
</A>
A TDR, directly connects TDI and TDO, bypassing BSR</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71967">
</A>
BSC<A NAME="marker=71966">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71969">
</A>
Boundary-scan cell</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71971">
</A>
Each I/O pad has a BSC to monitor signals</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71974">
</A>
BSR<A NAME="marker=71973">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71976">
</A>
Boundary-scan register</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71978">
</A>
A TDR, a shift register formed from a chain of BSCs</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71980">
</A>
BST</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71982">
</A>
Boundary-scan test</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71984">
</A>
Not to be confused with BIST (built-in self-test)</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71987">
</A>
IDCODE<A NAME="marker=71986">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71989">
</A>
Device-identification register</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71991">
</A>
Optional TDR, contains manufacturer and part number</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71994">
</A>
IR<A NAME="marker=71993">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71996">
</A>
Instruction register</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=71998">
</A>
Holds a BST instruction, provides control signals</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72001">
</A>
JTAG<A NAME="marker=72000">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72003">
</A>
Joint Test Action Group</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72005">
</A>
The organization that developed boundary scan</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72008">
</A>
TAP<A NAME="marker=72007">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72010">
</A>
Test-access port</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72012">
</A>
Four- (or five-)wire test interface to an ASIC</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72015">
</A>
TCK<A NAME="marker=72014">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72017">
</A>
Test clock</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72019">
</A>
A TAP wire, the clock that controls BST operation</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72022">
</A>
TDI<A NAME="marker=72021">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72024">
</A>
Test-data input</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72026">
</A>
A TAP wire, the input to the IR and TDRs</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72029">
</A>
TDO<A NAME="marker=72028">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72031">
</A>
Test-data output</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72033">
</A>
A TAP wire, the output from the IR and TDRs</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72036">
</A>
TDR<A NAME="marker=72035">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72038">
</A>
Test-data register</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72040">
</A>
Group of BST registers: IDCODE, BR, BSR</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72043">
</A>
TMS<A NAME="marker=72042">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72045">
</A>
Test-mode select</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72047">
</A>
A TAP wire, together with TCK controls the BST state</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72050">
</A>
TRST*<A NAME="marker=72049">
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