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<TITLE> 14.7 Built-in Self-test</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
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<H1 CLASS="Heading1">
<A NAME="pgfId=2625">
</A>
14.7 <A NAME="34679">
</A>
Built-in Self-test</H1>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=82319">
</A>
The trend to include more test logic on an ASIC has already been mentioned. <A NAME="marker=27360">
</A>
<SPAN CLASS="Definition">
Built-in self-test</SPAN>
(<A NAME="marker=27361">
</A>
<SPAN CLASS="Definition">
BIST</SPAN>
<A NAME="marker=27362">
</A>
) is a set of structured-test techniques for combinational and sequential logic, memories, multipliers, and other embedded logic blocks. In each case the principle is to generate test vectors, apply them to the <A NAME="marker=82332">
</A>
<SPAN CLASS="Definition">
circuit under test</SPAN>
(<A NAME="marker=82333">
</A>
<SPAN CLASS="Definition">
CUT</SPAN>
<A NAME="marker=82334">
</A>
) or <A NAME="marker=82316">
</A>
<SPAN CLASS="Definition">
device under test</SPAN>
(<A NAME="marker=82317">
</A>
<SPAN CLASS="Definition">
DUT</SPAN>
<A NAME="marker=82318">
</A>
), and then check the response.</P>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=20794">
</A>
14.7.1 <A NAME="18077">
</A>
LFSR</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=20801">
</A>
<A HREF="CH14.7.htm#36107" CLASS="XRef">
Figure 14.23</A>
shows a <A NAME="marker=20798">
</A>
<SPAN CLASS="Definition">
linear feedback shift register</SPAN>
(<A NAME="marker=20799">
</A>
<SPAN CLASS="Definition">
LFSR</SPAN>
<A NAME="marker=20800">
</A>
). The exclusive-OR gates and shift register act to produce a <A NAME="marker=20802">
</A>
<SPAN CLASS="Definition">
pseudorandom binary sequence</SPAN>
(<A NAME="marker=20803">
</A>
<A NAME="marker=20804">
</A>
<SPAN CLASS="Definition">
PRBS</SPAN>
<A NAME="marker=101869">
</A>
) at each of the flip-flop outputs. By correctly choosing the points at which we take the feedback from an <SPAN CLASS="EquationVariables">
n</SPAN>
-bit shift register (see <A HREF="CH14.7.htm#36532" CLASS="XRef">
Section 14.7.5</A>
), we can produce a PRBS of length 2<SUP CLASS="SuperscriptVariable">
n</SUP>
– 1, a <SPAN CLASS="Definition">
maximal-length sequence</SPAN>
<A NAME="marker=20806">
</A>
that includes all possible patterns (or vectors) of <SPAN CLASS="EquationVariables">
n</SPAN>
bits, excluding the all-zeros pattern. </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigTitleSide">
<A NAME="pgfId=84196">
</A>
FIGURE 14.23 <A NAME="36107">
</A>
A linear feedback shift register (LFSR). A 3-bit maximal-length LFSR produces a repeating string of seven pseudorandom binary numbers: 7, 3, 1, 4, 2, 5, 6. </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=84186">
</A>
</P>
<DIV>
<IMG SRC="CH14-25.gif">
</DIV>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=82342">
</A>
<A HREF="CH14.7.htm#39749" CLASS="XRef">
Table 14.10</A>
shows the maximal-length sequence, with length 2<SUP CLASS="Superscript">
3</SUP>
– 1 = 7, for the 3-bit LFSR shown in <A HREF="CH14.7.htm#36107" CLASS="XRef">
Figure 14.23</A>
. Notice that the first (clock tick 1) and last rows (clock tick 8) are identical. Rows following the seventh row repeat rows 1–7, so that the length of this 3-bit LFSR sequence is 7 = 2<SUP CLASS="Superscript">
3</SUP>
– 1, the maximal length. The shaded regions show how bits are shifted from one clock cycle to the next. We assume the register is initialized to the all-ones state, but any initial state will work and produce the same PRBS, as long as the initial state is not all zeros (in which case the LFSR will stay stuck at all zeros). </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="5">
<P CLASS="TableTitle">
<A NAME="pgfId=82352">
</A>
TABLE 14.10 <A NAME="39749">
</A>
LFSR example of <A HREF="CH14.7.htm#36107" CLASS="XRef">
Figure 14.23</A>
. </P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=82360">
</A>
Clock tick, t =</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=82362">
</A>
Q0<SUB CLASS="Subscript">
t+1</SUB>
= Q1<SUB CLASS="Subscript">
t</SUB>
<SPAN CLASS="Symbol">
⊕</SPAN>
Q2<SUB CLASS="Subscript">
t</SUB>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=82364">
</A>
Q1<SUB CLASS="Subscript">
t+1</SUB>
= Q0<SUB CLASS="Subscript">
t</SUB>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=82366">
</A>
Q2<SUB CLASS="Subscript">
t+1</SUB>
= Q1<SUB CLASS="Subscript">
t</SUB>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=84135">
</A>
Q0Q1Q2</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82368">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82370">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82372">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82374">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=84137">
</A>
7</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82376">
</A>
2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82378">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82380">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82382">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=84139">
</A>
3</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82384">
</A>
3</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82386">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82388">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82390">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=84141">
</A>
1</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82392">
</A>
4</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82394">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82396">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82398">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=84143">
</A>
4</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82400">
</A>
5</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82402">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82404">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82406">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=84145">
</A>
2</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82408">
</A>
6</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82410">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82412">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82414">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=84147">
</A>
5</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82416">
</A>
7</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82418">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82420">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82422">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=84149">
</A>
6</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82424">
</A>
8</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82426">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82428">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=82430">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=84151">
</A>
7</P>
</TD>
</TR>
</TABLE>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=82433">
</A>
14.7.2 <A NAME="35019">
</A>
Signature Analysis</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=15174">
</A>
<A HREF="CH14.7.htm#17123" CLASS="XRef">
Figure 14.24</A>
shows the LFSR of <A HREF="CH14.7.htm#36107" CLASS="XRef">
Figure 14.23</A>
with an additional XOR gate used in the first stage of the shift register. If we apply a binary input sequence to <SPAN CLASS="BodyComputer">
IN</SPAN>
, the shift register will perform <SPAN CLASS="Definition">
data compaction</SPAN>
<A NAME="marker=20741">
</A>
(or <SPAN CLASS="Definition">
compression</SPAN>
<A NAME="marker=68526">
</A>
) on the input sequence. At the end of the input sequence the shift-register contents, <SPAN CLASS="BodyComputer">
Q0Q1Q2</SPAN>
, will form a pattern that we call a <SPAN CLASS="Definition">
signature</SPAN>
<A NAME="marker=20742">
</A>
. If the input sequence and the <SPAN CLASS="Definition">
serial-input signature register</SPAN>
<A NAME="marker=87166">
</A>
(<SPAN CLASS="Definition">
SISR</SPAN>
<A NAME="marker=87167">
</A>
<A NAME="marker=87168">
</A>
) are long enough, it is unlikely (though possible) that two different input sequences will produce the same signature. If the input sequence comes from logic that we wish to test, a fault in the logic will cause the input sequence to change. This causes the signature to change from a known good value and we shall then know that the circuit under test is bad. This technique, called <A NAME="marker=20775">
</A>
<SPAN CLASS="Definition">
signature analysis</SPAN>
, was developed by <A NAME="marker=82464">
</A>
Hewlett-Packard to test equipment in the field in the late 1970s. </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigTitleSide">
<A NAME="pgfId=18042">
</A>
FIGURE 14.24 <A NAME="17123">
</A>
A 3-bit serial-input signature register (SISR) using an LFSR (linear feedback shift register). The LFSR is initialized to Q1Q2Q3 = '000' using the common RES (reset) signal. The signature, Q1Q2Q3, is formed from shift-and-add operations on the sequence of input bits (IN).</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=15171">
</A>
</P>
<DIV>
<IMG SRC="CH14-26.gif">
</DIV>
</TD>
</TR>
</TABLE>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=18071">
</A>
14.7.3 <A NAME="35362">
</A>
A Simple BIST Example</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=83574">
</A>
We can combine the PRBS generator of <A HREF="CH14.7.htm#36107" CLASS="XRef">
Figure 14.23</A>
together with the signature register of <A HREF="CH14.7.htm#17123" CLASS="XRef">
Figure 14.24</A>
to form the simple BIST structure shown in <A HREF="CH14.7.htm#11447" CLASS="XRef">
Figure 14.25</A>
(a). LFSR1 generates a maximal-length (2<SUP CLASS="Superscript">
3</SUP>
– 1 = 7 cycles) PRBS. LFSR2 computes the signature ('011' for the good circuit) of the CUT. LFSR1 is initialized to '100' (Q0 = 1, Q1 = 0, Q2 = 0) and LFSR2 is initialized to '000'. The schematic in <A HREF="CH14.7.htm#11447" CLASS="XRef">
Figure 14.25</A>
(a) shows the bit sequences in the circuit, both for a good circuit and for a bad circuit with a stuck-at-1 fault, F1. <A HREF="CH14.7.htm#11447" CLASS="XRef">
Figure 14.25</A>
(b) shows how the bit sequences are calculated in the good circuit. The signature is formed as R0R1R2 seven clock edges (on the eighth clock cycle) after the active-low reset is taken high. <A HREF="CH14.7.htm#13228" CLASS="XRef">
Figure 14.26</A>
shows the waveforms in the good and bad circuit. The bad circuit signature, '000', differs from the good circuit and the signature can either be compared with the known good signature on-chip or the signature may be shifted out and compared off-chip (both approaches are used in practice).</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="7">
<P CLASS="Table">
<A NAME="pgfId=83603">
</A>
(a)</P>
<DIV>
<IMG SRC="CH14-27.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="7">
<P CLASS="Table">
<A NAME="pgfId=83617">
</A>
(b)</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=83631">
</A>
Q0<SUB CLASS="Subscript">
t+1</SUB>
= </P>
<P CLASS="TableFirst">
<A NAME="pgfId=83632">
</A>
Q1<SUB CLASS="Subscript">
t</SUB>
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