ch14.3.htm

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<A NAME="pgfId=49998">
 </A>
The <A NAME="marker=49997">
 </A>
<SPAN CLASS="Definition">
single stuck-at fault</SPAN>
 (<SPAN CLASS="Definition">
SSF</SPAN>
<A NAME="marker=71292">
 </A>
<A NAME="marker=71293">
 </A>
) model assumes that there is just one fault in the logic we are testing. We use a single stuck-at fault model because a <A NAME="marker=49999">
 </A>
<SPAN CLASS="Definition">
multiple stuck-at fault model</SPAN>
 that could handle several faults in the logic at the same time is too complicated to implement. We hope that any multiple faults are caught by single stuck-at fault tests <A NAME="[Agarwal and Fung, 1981]">
 </A>
[Agarwal and Fung, 1981; <A NAME="[Hughes, 1986]">
 </A>
Hughes and McCluskey, 1986]. In practice this seems to be true.</P>
<P CLASS="Body">
<A NAME="pgfId=73406">
 </A>
There are other fault models. For example, we can assume that faults are located in the transistors using a <A NAME="marker=73407">
 </A>
<SPAN CLASS="Definition">
stuck-on fault</SPAN>
 and <A NAME="marker=73408">
 </A>
<SPAN CLASS="Definition">
stuck-open fault</SPAN>
 (or <SPAN CLASS="Definition">
stuck-off fault</SPAN>
<A NAME="marker=73409">
 </A>
). Fault models such as these are more realistic in that they more closely model the actual physical faults. However, in practice the simple SSF model has been found to work&#8212;and work well. We shall concentrate on the SSF model.</P>
<P CLASS="Body">
<A NAME="pgfId=73410">
 </A>
In the SSF model we further assume that the effect of the physical fault (whatever it may be) is to create only two kinds of logical fault. The two types of logical faults or <A NAME="marker=73411">
 </A>
<SPAN CLASS="Definition">
stuck-at faults</SPAN>
 are: a <A NAME="marker=73412">
 </A>
<SPAN CLASS="Definition">
stuck-at-1 fault</SPAN>
 (abbreviated to <A NAME="marker=73413">
 </A>
SA1 or <A NAME="marker=73414">
 </A>
s@1) and a <A NAME="marker=73415">
 </A>
<SPAN CLASS="Definition">
stuck-at-0 fault</SPAN>
 (<A NAME="marker=73416">
 </A>
SA0 or <A NAME="marker=73417">
 </A>
s@0). We say that we <A NAME="marker=73418">
 </A>
<SPAN CLASS="Definition">
place faults</SPAN>
 (<SPAN CLASS="Definition">
inject faults</SPAN>
, <SPAN CLASS="Definition">
seed faults</SPAN>
<A NAME="marker=73419">
 </A>
, or <A NAME="marker=73420">
 </A>
<SPAN CLASS="Definition">
apply faults</SPAN>
) on a node (or net), on an input of a circuit, or on an output of a circuit. The location at which we place the fault is the <A NAME="marker=73421">
 </A>
<SPAN CLASS="Definition">
fault origin</SPAN>
.</P>
<P CLASS="Body">
<A NAME="pgfId=50019">
 </A>
A <A NAME="marker=50018">
 </A>
<SPAN CLASS="Definition">
net fault </SPAN>
forces all the logic cell inputs that the net drives to a logic <SPAN CLASS="BodyComputer">
'1'</SPAN>
 or <SPAN CLASS="BodyComputer">
'0'</SPAN>
. An <A NAME="marker=50020">
 </A>
<SPAN CLASS="Definition">
input fault</SPAN>
 attached to a logic cell input forces the logic cell input to a <SPAN CLASS="BodyComputer">
'1'</SPAN>
 or <SPAN CLASS="BodyComputer">
'0'</SPAN>
, but does not affect other logic cell inputs on the same net. An <A NAME="marker=50021">
 </A>
<SPAN CLASS="Definition">
output fault</SPAN>
 attached to the output of a logic cell can have different strengths. If an output fault is a <A NAME="marker=50022">
 </A>
<SPAN CLASS="Definition">
supply-strength fault</SPAN>
 (or <SPAN CLASS="Definition">
rail-strength</SPAN>
<A NAME="marker=50023">
 </A>
 fault) the logic-cell output node and every other node on that net is forced to a <SPAN CLASS="BodyComputer">
'1'</SPAN>
 or <SPAN CLASS="BodyComputer">
'0'</SPAN>
&#8212;as if all these nodes were connected to one of the supply rails. An alternative assigns the same strength to the output fault as the drive strength of the logic cell. This allows contention between outputs on a net driving the same node. There is no standard method of handling <A NAME="marker=50024">
 </A>
<SPAN CLASS="Definition">
output-fault strength</SPAN>
, and no standard for using types of stuck-at faults. Usually we do not inject net faults; instead we inject only input faults and output faults. Some people use the term <A NAME="marker=73371">
 </A>
<SPAN CLASS="Definition">
node fault</SPAN>
&#8212;but in different ways to mean either a net fault, input fault, or output fault.</P>
<P CLASS="Body">
<A NAME="pgfId=50029">
 </A>
We usually inject stuck-at faults to the inputs and outputs, the pins, of logic cells (AND gates, OR gates, flip-flops, and so on). We do not inject faults to the internal nodes of a flip-flop, for example. We call this a <SPAN CLASS="Definition">
pin-fault model</SPAN>
<A NAME="marker=71301">
 </A>
 and say the fault level is at the <A NAME="marker=50031">
 </A>
<SPAN CLASS="Definition">
structural level</SPAN>
, <A NAME="marker=50032">
 </A>
gate level, or <A NAME="marker=50033">
 </A>
cell level. We could apply faults to the internal logic of a logic cell (such as a flip-flop) and (the fault level would then be at the <A NAME="marker=73432">
 </A>
transistor level or <A NAME="marker=73433">
 </A>
switch level. We do not use transistor-level or switch-level fault models because there is often no need. From experience, but not from any theoretical reason, it turns out that using a fault model that applies faults at the logic-cell level is sufficient to catch the bad chips in a production test.</P>
<P CLASS="Body">
<A NAME="pgfId=50035">
 </A>
When a fault changes the circuit behavior, the change is called the <A NAME="marker=50034">
 </A>
<SPAN CLASS="Definition">
fault effect</SPAN>
. Fault effects travel through the circuit to other logic cells causing other fault effects. This phenomenon is <A NAME="marker=50036">
 </A>
<SPAN CLASS="Definition">
fault propagation</SPAN>
. If the fault level is at the structural level, the phenomenon is <A NAME="marker=50037">
 </A>
<SPAN CLASS="Definition">
structural fault propagation</SPAN>
. If we have one or more large functional blocks in a design, we want to apply faults to the functional blocks only at the inputs and outputs of the blocks. We do not want to place (or cannot place) faults inside the blocks, but we do want faults to propagate through the blocks. This is <A NAME="marker=50038">
 </A>
<SPAN CLASS="Definition">
behavioral fault propagation</SPAN>
.</P>
<P CLASS="Body">
<A NAME="pgfId=50039">
 </A>
Designers adjust the fault level to the appropriate level at which they think there may be faults. Suppose we are performing a fault simulation on a board and we have already tested the chips. Then we might set the fault level to the chip level, placing faults only at the chip pins. For ASICs we use the logic-cell level. You have to be careful, though, if you mix behavioral level and structural level models in a <A NAME="marker=50043">
 </A>
<SPAN CLASS="Definition">
mixed-level fault simulation</SPAN>
. You need to be sure that the behavioral models propagates faults correctly. In particular, if the behavioral model responds to faults on its inputs by propagating too many unknown <SPAN CLASS="BodyComputer">
'X'</SPAN>
 values to its outputs, this will decrease the fault coverage, because the model is hiding the logic beyond it.</P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=55542">
 </A>
14.3.5&nbsp;Logical Faults</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=55687">
 </A>
<A HREF="CH14.3.htm#36716" CLASS="XRef">
Figure&nbsp;14.12</A>
 and the following list show how the defects and physical faults of <A HREF="CH14.3.htm#22772" CLASS="XRef">
Figure&nbsp;14.11</A>
 translate to logical faults (not all physical faults translate to logical faults&#8212;most do not):</P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=72445">
 </A>
F1 translates to node n1 being stuck at 0, equivalent to A1 being stuck at 1.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=72446">
 </A>
F2 will probably result in node n1 remaining high, equivalent to A1 being stuck at 0.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=72447">
 </A>
F3 will affect half of the <SPAN CLASS="Emphasis">
n</SPAN>
-channel pull-down stack and may result in a degradation fault, depending on what happens to the floating gate of T3. The cell will still work, but the fall time at the output will approximately double. A fault such as this in the middle of a chain of logic is extremely hard to detect.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=72448">
 </A>
F4 is a bridging fault whose effect depends on the relative strength of the transistors driving this node. The fault effect is not well modeled by a stuck-at fault model.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=72449">
 </A>
F5 completely disables half of the <SPAN CLASS="Emphasis">
n</SPAN>
-channel pulldown stack and will result in a degradation fault.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=72450">
 </A>
F6 shorts the output node to VDD and is equivalent to Z1 stuck at 1.</LI>
<LI CLASS="BulletLast">
<A NAME="pgfId=72451">
 </A>
Fault F7 could result in infant mortality. If this line did break due to electromigration the cell could no longer pull Z1 up to VDD. This would translate to a Z1 stuck at 0. This fault would probably be fatal and stop the ASIC working.</LI>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=55693">
 </A>
<IMG SRC="CH14-13.gif" ALIGN="BASELINE">
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=55695">
 </A>
FIGURE&nbsp;14.12&nbsp;<A NAME="36716">
 </A>
Fault models. (a) Physical faults at the layout level (problems during fabrication) shown in <A HREF="CH14.3.htm#22772" CLASS="XRef">
Figure&nbsp;14.11</A>
 translate to electrical problems on the detailed circuit schematic. The location and effect of fault F1 is shown. The locations of the other fault examples from <A HREF="CH14.3.htm#22772" CLASS="XRef">
Figure&nbsp;14.11</A>
 (F2&#8211;F6) are shown, but not their effect. (b)&nbsp;We can translate some of these faults to the simplified transistor schematic. (c)&nbsp;Only a few of the physical faults still remain in a gate-level fault model of the logic cell. (d)&nbsp;Finally at the functional-level fault model of a logic cell, we abandon the connection between physical and logical faults and model all faults by stuck-at faults. This is a very poor model of the physical reality, but it works well in practice.</P>
</TD>
</TR>
</TABLE>
</UL>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=73623">
 </A>
14.3.6&nbsp;<A NAME="28562">
 </A>
IDDQ Test</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=73624">
 </A>
When they receive a prototype ASIC, experienced designers measure the resistance between VDD and GND pins. Providing there is not a short between VDD and GND, they connect the power supplies and measure the power-supply current. From experience they know that a supply current of more than a few milliamperes indicates a bad chip. This is exactly what we want in production test: Find the bad chips quickly, get them off the tester, and save expensive tester time. An <SPAN CLASS="Definition">
IDDQ</SPAN>
<A NAME="marker=73625">
 </A>
 (IDD<A NAME="marker=73626">
 </A>
 stands for the supply current, and Q stands for quiescent) test is one of the first production tests applied to a chip on the tester, after the chip logic has been initialized [<A NAME="[Gulati and Hawkins, 1993]">
 </A>
Gulati and Hawkins, 1993; <A NAME="Rajsuman, 1994">
 </A>
Rajsuman, 1994]. High supply current can result from bridging faults that we described in <A HREF="CH14.3.htm#16310" CLASS="XRef">
Section&nbsp;14.3.2</A>
. For example, the bridging fault F4 in <A HREF="CH14.3.htm#22772" CLASS="XRef">
Figure&nbsp;14.11</A>
 and <A HREF="CH14.3.htm#36716" CLASS="XRef">
Figure&nbsp;14.12</A>
 would cause excessive IDDQ if node n1 and input B1 are being driven to opposite values.</P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=50047">
 </A>
14.3.7&nbsp;Fault Collapsing</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=56001">
 </A>
<A HREF="CH14.3.htm#35252" CLASS="XRef">
Figure&nbsp;14.13</A>
(a) shows a test for a stuck-at-1 output of a two-input NAND gate. <A HREF="CH14.3.htm#35252" CLASS="XRef">
Figure&nbsp;14.13</A>
(b) shows tests for other stuck-at faults. We assume that the NAND gate still works correctly in the <SPAN CLASS="Definition">
bad circuit</SPAN>
<A NAME="marker=73973">
 </A>
 (also called the <SPAN CLASS="Definition">
faulty circuit</SPAN>
<A NAME="marker=73974">
 </A>
 or <SPAN CLASS="Definition">
faulty machine</SPAN>
<A NAME="marker=73975">
 </A>
) even if we have an input fault. The input fault on a logic cell is presumed to arise either from a fault from a preceding logic cell or a fault on the connection to the input. </P>
<P CLASS="Body">
<A NAME="pgfId=73905">
 </A>
Stuck-at faults attached to different points in a circuit may produce identical fault effects. Using <A NAME="marker=56002">
 </A>
<SPAN CLASS="Definition">
fault collapsing</SPAN>
 we can group these <A NAME="marker=56003">
 </A>
<SPAN CLASS="Definition">
equivalent faults</SPAN>
 (or <SPAN CLASS="Definition">
indistinguishable faults</SPAN>
<A NAME="marker=74658">
 </A>
) into a <A NAME="marker=56004">
 </A>
<SPAN CLASS="Definition">
fault-equivalence class</SPAN>
. To save time we need only consider one fault, called the <A NAME="marker=56005">
 </A>
<SPAN CLASS="Definition">
prime fault</SPAN>
 or <SPAN CLASS="Definition">
representative fault</SPAN>
<A NAME="marker=56006">
 </A>
, from a fault-equivalence class. For example, <A HREF="CH14.3.htm#35252" CLASS="XRef">
Figure&nbsp;14.13</A>
(a) and (b) show that a stuck-at-0 input and a stuck-at-1 output are equivalent faults for a two-input NAND gate. We only need to check for one fault, Z1 (output stuck at 1), to catch any of the equivalent faults. </P>
<P CLASS="Body">
<A NAME="pgfId=71361">
 </A>
Suppose that any of the tests that detect a fault B also detects fault A, but only some of the tests for fault A also detect fault B. W say A is a <A NAME="marker=50060">
 </A>
<SPAN CLASS="Definition">
dominant fault</SPAN>
, or that fault A dominates fault B (this the definition of fault dominance that we shall use, some texts say fault B dominates fault A in this situation). Clearly to reduce the number of tests using <A NAME="marker=50061">
 </A>
<SPAN CLASS="Definition">
dominant fault collapsing</SPAN>
 we will pick the test for fault B. For example, <A HREF="CH14.3.htm#35252" CLASS="XRef">
Figure&nbsp;14.13</A>
(c) shows that the output stuck at 0 dominates either input stuck at 1 for a two-input NAND. By testing for fault A1, we automatically detect the fault Z1. Confusion over dominance arises because of the difference between focusing on faults (<A HREF="CH14.3.htm#35252" CLASS="XRef">
Figure&nbsp;14.13</A>
d) or test vectors (<A HREF="CH14.3.htm#35252" CLASS="XRef">
Figure&nbsp;14.13</A>
e).</P>
<P CLASS="Body">
<A NAME="pgfId=105510">
 </A>
<A HREF="CH14.3.htm#35252" CLASS="XRef">
Figure&nbsp;14.13</A>
(f) shows the six stuck-at faults for a two-input NAND gate. We can place SA1 or SA0 on each of the two input pins (four faults in total) and SA1 or SA0 on the output pins. Using fault equivalence (<A HREF="CH14.3.htm#35252" CLASS="XRef">
Figure&nbsp;14.13</A>
g) we can collapse six faults to four: SA1 on each input, and SA1 or SA0 on the output. Using fault dominance (<A HREF="CH14.3.htm#35252" CLASS="XRef">
Figure&nbsp;14.13</A>
h) we can collapse six faults to three. There is no way to tell the difference between equivalent faults, but if we use dominant fault collapsing we may lose information about the fault location.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=105524">
 </A>
<IMG SRC="CH14-14.gif" ALIGN="BASELINE">
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=105528">
 </A>
FIGURE&nbsp;14.13&nbsp;<A NAME="35252">
 </A>
Fault dominance and fault equivalence. (a)&nbsp;We can test for fault Z0 (Z stuck at 0) by applying a test vector that makes the bad (faulty) circuit produce a different output than the good circuit. (b)&nbsp;Some test vectors provide tests for more than one fault. (c)&nbsp;A test for A stuck at 1 (A1) will also test for Z stuck at 0; Z0 dominates A1. The fault effects of faults: A0, B0 and Z1 are the same. These faults are equivalent. (d)&nbsp;There are six sets of input vectors that test for the six stuck-at faults. (e)&nbsp;We only need to choose a subset of all test vectors that test for all faults. (f)&nbsp;The six stuck-at faults for a two-input NAND logic cell. (g)&nbsp;Using fault equivalence we can collapse six faults to four. (h)&nbsp;Using fault dominance we can collapse six faults to three. </P>
</TD>
</TR>
</TABLE>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=105529">
 </A>
14.3.8&nbsp;Fault-Collapsing Example</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=105534">
 </A>
<A HREF="CH14.3.htm#16029" CLASS="XRef">
Figure&nbsp;14.14</A>
 shows an example of fault collapsing. Using the properties of logic cells to reduce the number of faults that we need to consider is called <A NAME="marker=105535">
 </A>
<SPAN CLASS="Definition">
gate collapsing</SPAN>
. We can also use <A NAME="marker=105536">
 </A>
<SPAN CLASS="Definition">
node collapsing</SPAN>
 by examining the effect of faults on the same node. Consider two inverters in series. An output fault on the first inverter collapses with the node fault on the net connecting the inverters. We can collapse the node fault in turn with the input fault of the second inverter. The details of fault collapsing depends on whether the simulator uses net or pin faults, the fanin and fanout of nodes, and the output fault-strength model used.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=105542">
 </A>
&nbsp;</P>
<DIV>
<IMG SRC="CH14-15.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=105546">
 </A>
FIGURE&nbsp;14.14&nbsp;<A NAME="16029">
 </A>
Fault collapsing for A'B + BC. (a)&nbsp;A pin-fault model. Each pin has stuck-at-0 and stuck-at-1 faults. (b)&nbsp;Using fault equivalence the pin faults at the input pins and output pins of logic cells are collapsed. This is gate collapsing. (c)&nbsp;We can reduce the number of faults we need to consider further by collapsing equivalent faults on nodes and between logic cells. This is node collapsing. (d)&nbsp;The final circuit has eight stuck-at faults (reduced from the 22 original faults). If we wished to use fault dominance we could also eliminate the stuck-at-0 fault on Z. Notice that in a pin-fault model we cannot collapse the faults U4.A1.SA1 and U3.A2.SA1 even though they are on the same net.</P>
</TD>
</TR>
</TABLE>
</DIV>
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