ch14.3.htm
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Surface contamination, moisture</P>
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Metal migration, stress, peeling</P>
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Metallization (open or short)</P>
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Gate</P>
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Contact opens</P>
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Gate to S/D junction short</P>
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Field-oxide parasitic device</P>
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Gate-oxide imperfection, spiking</P>
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Mask misalignment</P>
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A <A NAME="marker=49975">
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<SPAN CLASS="Definition">
degradation fault</SPAN>
may be a <A NAME="marker=49976">
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<SPAN CLASS="Definition">
parametric fault</SPAN>
or <SPAN CLASS="Definition">
delay fault</SPAN>
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(<SPAN CLASS="Definition">
timing fault</SPAN>
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). A parametric fault might lead to an incorrect switching threshold in a TTL/CMOS level converter at an input, for example. We can test for parametric faults using a production tester. A <SPAN CLASS="Definition">
delay fault</SPAN>
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</A>
might lead to a critical path being slower than specification. Delay faults are much harder to test in production. An <SPAN CLASS="Definition">
open-circuit fault</SPAN>
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results from physical faults such as a bad contact, a piece of metal that is missing or overetched, or a break in a polysilicon line. These physical faults all result in failure to transmit a logic level from one part of a circuit to another—an open circuit. A <SPAN CLASS="Definition">
short-circuit fault</SPAN>
<A NAME="marker=49985">
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results from such physical faults as: underetching of metal; spiking, pinholes or shorts across the gate oxide; and diffusion shorts. These faults result in a circuit being accidentally connected—a short circuit. Most short-circuit faults occur in interconnect; often we call these <A NAME="marker=49987">
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<SPAN CLASS="Definition">
bridging faults</SPAN>
(BF). A BF usually results from <A NAME="marker=49988">
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<SPAN CLASS="Definition">
metal coverage</SPAN>
problems that lead to shorts. You may see reference to <SPAN CLASS="Definition">
feedback bridging faults</SPAN>
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and <SPAN CLASS="Definition">
nonfeedback bridging faults</SPAN>
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, a useful distinction when trying to predict the results of faults on logic operation. Bridging faults are a frequent problem in CMOS ICs. </P>
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14.3.3 Physical Faults</H2>
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<A HREF="CH14.3.htm#22772" CLASS="XRef">
Figure 14.11</A>
shows the following examples of physical faults in a logic cell:</P>
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<IMG SRC="CH14-12.gif">
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FIGURE 14.11 <A NAME="22772">
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Defects and physical faults. Many types of defects occur during fabrication. Defects can be of any size and on any layer. Only a few small sample defects are shown here using a typical standard cell as an example. Defect density for a modern CMOS process is of the order of 1 cm<SUP CLASS="Superscript">
–2</SUP>
or less across a whole wafer. The logic cell shown here is approximately 64 <SPAN CLASS="Symbol">
¥</SPAN>
32 <SPAN CLASS="Symbol">
l</SPAN>
<SUP CLASS="Superscript">
2</SUP>
, or 250 <SPAN CLASS="Symbol">
m</SPAN>
m<SUP CLASS="Superscript">
2</SUP>
for a <SPAN CLASS="Symbol">
l </SPAN>
= 0.25 <SPAN CLASS="Symbol">
m</SPAN>
m process. We would thus have to examine approximately 1 cm<SUP CLASS="Superscript">
–2</SUP>
/250 <SPAN CLASS="Symbol">
m</SPAN>
m<SUP CLASS="Superscript">
2</SUP>
or 400,000 such logic cells to find a single defect. </P>
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F1 is a short between m1 lines and connects node n1 to VSS.</LI>
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F2 is an open on the poly layer and disconnects the gate of transistor t1 from the rest of the circuit.</LI>
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F3 is an open on the poly layer and disconnects the gate of transistor t3 from the rest of the circuit.</LI>
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F4 is a short on the poly layer and connects the gate of transistor t4 to the gate of transistor t5.</LI>
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F5 is an open on m1 and disconnects node n4 from the output Z1.</LI>
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F6 is a short on m1 and connects nodes p5 and p6.</LI>
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F7 is a nonfatal defect that causes necking on m1.</LI>
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Once we have reduced the large number of physical faults to fewer logical faults, we need a model to predict their effect. The most common model is the <SPAN CLASS="Definition">
stuck-at fault model</SPAN>
.</P>
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14.3.4 <A NAME="27645">
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Stuck-at Fault Model</H2>
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