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<TITLE> 14.3 Faults</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
<DIV>
<P>[ <A HREF="CH14.htm">Chapter start</A> ] [ <A HREF="CH14.2.htm">Previous page</A> ] [ <A HREF="CH14.4.htm">Next page</A> ]</P><!--#include file="AmazonAsic.html"--><HR></DIV>
<H1 CLASS="Heading1">
<A NAME="pgfId=49586">
</A>
14.3 <A NAME="21862">
</A>
Faults</H1>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=49587">
</A>
Fabrication of an ASIC is a complicated process requiring hundreds of processing steps. Problems may introduce a <A NAME="marker=49588">
</A>
<SPAN CLASS="Definition">
defect</SPAN>
that in turn may introduce a <A NAME="marker=49589">
</A>
<SPAN CLASS="Definition">
fault</SPAN>
(Sabnis [<A NAME="Sabnis, 1990">
</A>
1990] describes <SPAN CLASS="Definition">
defect mechanisms</SPAN>
<A NAME="marker=104907">
</A>
). Any problem during fabrication may prevent a transistor from working and may break or join interconnections. Two common types of defects occur in metallization [<A NAME="Rao, 1993">
</A>
Rao, 1993]: either underetching the metal (a problem between long, closely spaced lines), which results in a <SPAN CLASS="Definition">
bridge</SPAN>
<A NAME="marker=86846">
</A>
or short circuit (<SPAN CLASS="Definition">
shorts</SPAN>
<A NAME="marker=86847">
</A>
) between adjacent lines, or overetching the metal and causing <SPAN CLASS="Definition">
breaks</SPAN>
<A NAME="marker=86848">
</A>
or open circuits (<SPAN CLASS="Definition">
opens</SPAN>
<A NAME="marker=86849">
</A>
). Defects may also arise after chip fabrication is complete—while testing the wafer, cutting the die from the wafer, or mounting the die in a package. Wafer probing, wafer saw, die attach, wire bonding, and the intermediate handling steps each have their own defect and failure mechanisms. Many different materials are involved in the packaging process that have different mechanical, electrical, and thermal properties, and these differences can cause defects due to corrosion, stress, adhesion failure, cracking, and peeling. Yield loss also occurs from human error—using the wrong mask, incorrectly setting the implant dose—as well as from physical sources: contaminated chemicals, dirty etch sinks, or a troublesome process step. It is possible to repeat or <SPAN CLASS="Definition">
rework</SPAN>
<A NAME="marker=73480">
</A>
some of the reversible steps (a lithography step, for example—but not etching) if there are problems. However, reliance on rework indicates a poorly controlled process.</P>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=55512">
</A>
14.3.1 Reliability </H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=55513">
</A>
It is possible for defects to be nonfatal but to cause failures early in the life of a product. We call this <A NAME="marker=55514">
</A>
<SPAN CLASS="Definition">
infant mortality</SPAN>
. Most products follow the same kinds of trend for failures as a function of life. Failure rates decrease rapidly to a low value that remains steady until the end of life when failure rates increase again; this is called a <A NAME="marker=55515">
</A>
<SPAN CLASS="Definition">
bathtub curve</SPAN>
. The end of a product lifetime is determined by various <SPAN CLASS="Definition">
wearout mechanisms</SPAN>
<A NAME="marker=73533">
</A>
(usually these are controlled by an exponential energy process). Some of the most important wearout mechanisms in ASICs are <A NAME="marker=73514">
</A>
hot-electron wearout, <A NAME="marker=55516">
</A>
electromigration, and the failure of antifuses in FPGAs.</P>
<P CLASS="Body">
<A NAME="pgfId=55517">
</A>
We can catch some of the products that are susceptible to early failure using <SPAN CLASS="Definition">
burn-in</SPAN>
<A NAME="marker=72291">
</A>
. Many failure mechanisms have a failure rate proportional to exp (–<SPAN CLASS="EquationVariables">
E</SPAN>
<SUB CLASS="SubscriptVariable">
a</SUB>
/kT). This is the <SPAN CLASS="Definition">
Arrhenius equation</SPAN>
<A NAME="marker=73487">
</A>
, where <SPAN CLASS="EquationVariables">
E</SPAN>
<SUB CLASS="SubscriptVariable">
a</SUB>
is a known <SPAN CLASS="Definition">
activation energy</SPAN>
<A NAME="marker=73488">
</A>
(k is Boltzmann’s constant, 8.62 <SPAN CLASS="Symbol">
¥</SPAN>
10<SUP CLASS="Superscript">
–5</SUP>
eVK<SUP CLASS="Superscript">
-1</SUP>
, and T the absolute temperature). Operating an ASIC at an elevated temperature accelerates this type of failure mechanism. Depending on the physics of the failure mechanism, additional stresses, such as elevated current or voltage, may also accelerate failures. The longer and harsher the burn-in conditions, the more likely we are to find problems, but the more costly the process and the more costly the parts. </P>
<P CLASS="Body">
<A NAME="pgfId=55522">
</A>
We can measure the overall <A NAME="marker=55520">
</A>
<SPAN CLASS="Definition">
reliability</SPAN>
of any product using the <A NAME="marker=55521">
</A>
<SPAN CLASS="Definition">
mean time between failures</SPAN>
(<A NAME="marker=55523">
</A>
<SPAN CLASS="Definition">
MTBF</SPAN>
<A NAME="marker=73547">
</A>
) for a repairable product or <SPAN CLASS="Definition">
mean time to failure</SPAN>
<A NAME="marker=73551">
</A>
(<SPAN CLASS="Definition">
MTTF</SPAN>
<A NAME="marker=73552">
</A>
<A NAME="marker=73553">
</A>
) for a fatal failure. We also use <A NAME="marker=55524">
</A>
<SPAN CLASS="Definition">
failures in time</SPAN>
(<A NAME="marker=55525">
</A>
<SPAN CLASS="Definition">
FITs</SPAN>
<A NAME="marker=55526">
</A>
) where 1 FIT equals a single failure in 10<SUP CLASS="Superscript">
9</SUP>
hours. We can sum the FITs for all the components in a product to determine an overall measure for the product reliability. Suppose we have a system with the following components:</P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=55527">
</A>
Microprocessor (standard part) 5 FITs</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=55528">
</A>
100 TTL parts, 50 parts at 10 FITs, 50 parts at 15 FITs</LI>
<LI CLASS="BulletFirst">
<A NAME="pgfId=55529">
</A>
100 RAM chips, 6 FITs</LI>
</UL>
<P CLASS="Body">
<A NAME="pgfId=55530">
</A>
The overall failure rate for this system is 5 + 50<SPAN CLASS="Symbol">
</SPAN>
<SPAN CLASS="Symbol">
¥ </SPAN>
10 + 50<SPAN CLASS="Symbol">
</SPAN>
<SPAN CLASS="Symbol">
¥</SPAN>
<SPAN CLASS="Symbol">
</SPAN>
15 + 100<SPAN CLASS="Symbol">
</SPAN>
<SPAN CLASS="Symbol">
¥ </SPAN>
6 = 1855 FITs. Suppose we could reduce the component count using ASICs to the following:</P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=55531">
</A>
Microprocessor (custom) 7 FITs</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=55532">
</A>
9 ASICs, 10 FITs</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=55533">
</A>
5 SIMMs, 15 FITs</LI>
</UL>
<P CLASS="Body">
<A NAME="pgfId=55534">
</A>
The failure rate is now 10 + 9<SPAN CLASS="Symbol">
¥ </SPAN>
10 + 5<SPAN CLASS="Symbol">
¥ </SPAN>
15 = 175 FITs, or about an order of magnitude lower. This is the rationale behind the Sun SparcStation 1 design described in <A HREF="/Humuhumu/from Antibes/Prof.htm#37484" CLASS="XRef">
Section 1.3</A>
, “<A HREF="/Humuhumu/from Antibes/Prof.htm#37484" CLASS="XRef">
Case Study</A>
.”</P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=49802">
</A>
14.3.2 <A NAME="16310">
</A>
Fault Models</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=49806">
</A>
<A HREF="CH14.3.htm#16372" CLASS="XRef">
Table 14.6</A>
shows some of the causes of faults. The first column shows the <SPAN CLASS="Definition">
fault level</SPAN>
<A NAME="marker=73305">
</A>
—whether the fault occurs in the logic gates on the chip or in the package. The second column describes the <SPAN CLASS="Definition">
physical fault</SPAN>
<A NAME="marker=73306">
</A>
. There are too many of these and we need a way to reduce and simplify their effects—by using a fault model.</P>
<P CLASS="Body">
<A NAME="pgfId=49808">
</A>
There are several types of <A NAME="marker=49807">
</A>
<SPAN CLASS="Definition">
fault model</SPAN>
. First, we simplify things by mapping from a physical fault to a <SPAN CLASS="Definition">
logical fault</SPAN>
<A NAME="marker=55734">
</A>
. Next, we distinguish between those logical faults that degrade the ASIC performance and those faults that are fatal and stop the ASIC from working at all. There are three kinds of logical faults in <A HREF="CH14.3.htm#38343" CLASS="XRef">
Table 14.6</A>
: a <SPAN CLASS="Emphasis">
degradation</SPAN>
fault, an <SPAN CLASS="Emphasis">
open-circuit</SPAN>
fault, and a <SPAN CLASS="Emphasis">
short-circuit</SPAN>
fault. </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="5">
<P CLASS="TableTitle">
<A NAME="pgfId=55829">
</A>
TABLE 14.6 <A NAME="16372">
</A>
<A NAME="38343">
</A>
Mapping physical faults to logical faults.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=55839">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=55841">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="3">
<P CLASS="TableFirst">
<A NAME="pgfId=55843">
</A>
Logical fault</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=55849">
</A>
Fault level</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=55851">
</A>
<SPAN CLASS="TableHeads">
Physical fault</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=55853">
</A>
<SPAN CLASS="TableHeads">
Degradation fault</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=55855">
</A>
<SPAN CLASS="TableHeads">
Open-circuit fault</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=55857">
</A>
<SPAN CLASS="TableHeads">
Short-circuit fault</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=117812">
</A>
Chip</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=117814">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=117816">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=117818">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=117820">
</A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=55859">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=55861">
</A>
Leakage or short between package leads</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=55863">
</A>
•</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=55865">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=55867">
</A>
•</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=55869">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=55871">
</A>
Broken, misaligned, or poor wire bonding</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=55873">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=55875">
</A>
•</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=55877">
</A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=55879">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=55881">
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